1990-1992

- T. Sasao and P. Besslich, "On the complexity of MOD-2 Sum PLA's," IEEE Trans. on Comput. Vol. 39, No. 2, pp. 262-266, Feb. 1990. PDF
- T. Sasao, "Bounds on the average number of products in the minimum sum-of-products expressions for multiple-valued input two-valued output functions," IEEE Trans. on Comput. Vol. 40, No. 5, pp. 645-651 May 1991. PDF
- T. Sasao," EXMIN: A simplification algorithm for exclusive-or sum-of-products expressions for multiple-valued input two-valued output functions," Proceeding of the 20th International Symposium on Multiple-Valued Logic, Charlotte, North Carolina, pp. 128-135, May 1990. PDF
- T. Sasao, "A transformation of multiple-valued input two-valued output functions and its application to simplification of exclusive-or sum-of-products expressions," ISMVL-91, May 1991, pp. 270-279. PDF
- T. Sasao, "Optimization of multiple-valued AND-EXOR expressions using multiple-place decision diagrams," ISMVL-92, May 1992, pp. 451-458. PDF

- T. Sasao, "Multiple-valued decomposition of generalized Boolean functions and the complexity of programmable logic arrays," IEEE Trans. on Comput. Vol. C-30, No. 9, pp. 635-643, Sept. 1981. PDF
- T. Sasao, "Input variable assignment and output phase optimization of PLA's," IEEE Trans. on Comput. Vol. C-33, No. 10, pp. 879-894, Oct. 1984. PDF
- T. Sasao, "An algorithm to derive the complement of a binary function with multiple-valued inputs," IEEE Trans. on Comput. Vol. C-34, No. 2, pp. 131-140, Feb. 1985. PDF
- T. Sasao," Multiple-valued logic and optimization of programmable logic arrays," IEEE Computer, Vol. 21, No. 4, pp. 71-80, April 1988. PDF
- T. Sasao, "On the optimal design of multiple-valued PLA's," IEEE Trans. on Comput. Vol. 38. No. 4, pp. 582-592, April 1989. PDF
- T. Sasao, "MACDAS: Multi-level AND-OR circuit synthesis using two-variable function generators," 23rd ACM/IEEE Design Automation Conference, Las Vegas, pp. 86-93, June 1986. PDF
- T. Sasao, "Application of multiple-valued logic to a serial decomposition of PLA's," Proceedings of the 19th International Symposium on Multiple-Valued Logic, Gangzou, China, pp. 264-271, May 1989. PDF
- T. Sasao, " HART: A hardware for logic minimization and verification," International Conference on Computer Desigh: VLSI in Computer, Oct.7-10, 1985, Port Chester, NY, USA, pp. 713-718. PDF
- T. Sasao and H. Terada, "On the complexity of shallow logic functions and the estimation of programmable logic array size," Proceedings of the 10th International Symposium on Multiple- Valued Logic, Evanston, Illinois, pp. 65-73, June 1980. PDF
- T. Sasao, "An application of multiple-valued logic to a design of masterslice gate array LSI," Proceedings of the 12th International Symposium on Multiple-Valued Logic, Paris, pp. 45-54, May 1982. PDF
- T. Sasao, "A fast complementation algorithm for sum-of-products expressions of multiple-valued input binary functions," Proceedings of the 13th International Symposium on Multiple- Valued Logic, Kyoto, pp. 103-110, May 1983. PDF
- T. Sasao, "Tautology checking algorithm for multiple-valued input binary functions and their application," Proceedings of the 14th International Symposium on Multiple-Valued Logic, Winnipeg, Manitoba, Canada, pp. 242-250, May 1984. PDF
- T. Sasao, "On the optimal design of multiple-valued PLA's," Proceedings of the 16th International Symposium on Multiple-Valued Logic, Blacksburg, Virginia, pp. 214-223, May 1986. PDF
- T. Sasao, "Bounds on the average number of products in the minimal sum-of-products expressions for multiple-valued input two-valued output functions," Proceedings of the 17th International Symposium on Multiple-Valued Logic, Boston, pp. 260-267, May 1987. PDF
- T. Sasao, "Application of multiple-valued logic to a serial decomposition of PLA's," Proceedings of the 19th International Symposium on Multiple-Valued Logic, Gangzou, China, pp. 264-271, May 1989. PDF

- H. Fujiwara, Y. Nagao, T. Sasao and K. Kinoshita, "Easily testable sequential machine with extra inputs," IEEE Trans. on Comput., vol. C-24, No. 8, pp. 821-826, Aug. 1975.
- K. Kinoshita T. Sasao, and J. Matsuda, "On magnetic bubble logic circuits," IEEE Trans. on Comput. Vol. C-27, No.3, pp. 214-221, March 1976.
- T. Sasao and K. Kinoshita, "Cascade realization of 3-input 3-output conservative logic circuits," IEEE Trans. on Comput. Vol. C-27, No.3, pp. 214-221, March 1978. PDF
- T. Sasao and K. Kinoshita, "Realization of minimum circuits with two-input conservative logic elements," IEEE Trans. on Comput. Vol. C-27, No. 8, pp. 749-752, Aug. 1978. PDF
- T. Sasao and K. Kinoshita," On the number of fanout-free functions and unate cascade functions," IEEE Trans. on Comput. vol. C-28, No. 1, pp. 866-72, Jan. 1979. PDF
- T. Sasao and K. Kinoshita," Conservative logic elements and their universality," IEEE Trans. on Comput. vol. C-28, No. 9, pp. 682-685, Sept. 1979. PDF
- T. Sasao and K. Kinoshita, "Cascade realization of 3-input 3-output conservative logic elements --- Application of three-valued logic to two-valued logic----",Proceeding of the 6th International Symposium on Multiple-valued Logic, Utah, p.625, May 1976. PDF
- T. Sasao, "An application of multiple-valued logic to a design of programmable logic arrays," Proceedings of the 8th International Symposium on Multiple-Valued Logic, Rosemont, Illinois, pp. 65-72, May 1978. PDF
- T. Sasao and H. Terada, "Multiple-valued logic and the design of programmable logic arrays with decoders," Proceedings of the 9th International Symposium on Multiple-Valued Logic, Bath, England, pp. 27-37, May 1979. PDF

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