Publication 2005

• H. Qin, T. Sasao, and Y. Iguchi, "An FPGA design of AES encryption circuit with 128-bit keys," GLSVLSI 2005, Chicago, IL, April 17-19, 2005, pp. 147-151. PDF
• K. Nakamura, T. Sasao, M. Matsuura, K. Tanaka, K. Yoshizumi, H. Qin, and Y. Iguchi, "Programmable logic device with an 8-stage cascade of 64K-bit asynchronous SRAMs," Cool Chips VIII, IEEE Symposium on Low-Power and High-Speed Chips, April 20-22, 2005, Yokohama, Japan. PDF Slides
• T. Sasao,"Radix converters: Complexity and implementation by LUT cascades," ISMVL-2005, May 19-21, 2005, Calgary, Canada, pp.256-263. PDF
• Y. Iguchi and T. Sasao,"Hardware to compute Walsh coefficients," ISMVL-2005, May 19-21, 2005, Calgary, Canada, pp.75-81. (With Figures) PDF
• M. Perkowski, T. Sasao, J-H. Kim, M. Lukac, J. Allen, and S. Gebauer, "Hahoe KAIST robot theater: Learning rules of interactive robot behavior as a multi-valued logic synthesis problem," ISMVL-2005, May 19-21, 2005, Calgary, Canada, pp.236-248. PDF
• T. Sasao, "Analysis and synthesis of weighted-sum functions," International Workshop on Logic and Synthesis, Lake Arrowhead, CA, USA, June 8-10, 2005,pp.455-462. PDF
• T. Sasao and M. Matsuura, "BDD representation for incompletely specified multiple-output logic functions and its applications to functional decomposition," Design Automation Conference, June 2005, pp.373-378. PDF
• D. Debnath and T. Sasao," Output phase optimization for AND-OR-EXOR PLAs with decoders and its application to design of adders," in "Special Issue on Recent Advances in Circuits and Systems" of the IEICE Transactions on Information and Systems, Vol. E88-D. No. 7, July 2005, pp.1492-1500. PDF
• S. Nagayama, A. Mishchenko, T. Sasao, and Jon T. Butler, "Exact and heuristic minimization of the average path length in decision diagrams" Journal of Multiple-Valued Logic and Soft Computing, Vol.11, No.5-6, pp.437-465, Aug. 2005. PDF1 PDF2
• J. T. Butler, T. Sasao, and M. Matsuura, "Average path length of binary decision diagrams" IEEE Transactions on Computers, Vol. 54, No.9, pp.1041-1053, Sept. 2005. PDF
• T. Sasao, S. Nagayama, and J. T. Butler, "Programmable numerical function generators: Architectures and synthesis system," FPL2005 ,Tampere, Aug.24-26, 2005, pp.118-123. PDF
• T. Sasao, Y. Iguchi, T. Suzuki, "On LUT cascade realizations of FIR filters," DSD2005, 8th Euromicro Conference on Digital System Design: Architectures, Methods and Tools, Porto, Portugal, Aug. 30 - Sept. 3, 2005, pp.467-474. PDF
• K. Nakamura, T. Sasao, M. Matsuura, K. Tanaka, K. Yoshizumi, H. Nakahara, and Y. Iguchi, "A memory-based programmable logic device using a look-up table cascade with synchronous SRAMs,"2005 International Conference on Solid State Devices and Materials (SSDM 2005),Kobe, Japan, Sep. 2005. PDF
• T. Sasao, Y. Iguchi, M. Matsuura, "LUT cascades and emulators for realizations of logic functions," RM2005, Tokyo, Japan, Sept. 5 - Sept. 6, 2005, pp.63-70. PDF
• S. Nagayama, and T. Sasao, "On the optimization of heterogeneous MDDs," IEEE Transactions on CAD, Vol. 24, No.11, Nov. 2005, pp.1645-1659. PDF
• B. Falkowski and T. Sasao, "Unified algorithm to generate Walsh functions in four different orderings and its programmable hardware implementation," IEE Proc. Vision, Image & Signal Processing, Vol. 152, No.6, Dec. 2005, pp.819-826. PDF
• D. Debnath and T. Sasao, "Exact minimization of FPRMs for incompletely specified functions by using MTBDDs," IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, Vol. E88-A, No.12, Dec. 2005, pp.3332-3341. PDF
• H. Nakahara, T. Sasao, and M. Matsuura, "A design algorithm for sequential circuits using LUT rings," IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, Vol. E88-A, No.12, Dec. 2005, pp.3342-3350. PDF