Publication 2006

• S. Nagayama, T. Sasao, and J. T. Butler, "Programmable numerical function generators based on quadratic approximation: Architecture and synthesis method," ASPDAC 2006, Yokohama Jan. 2006, pp. 378-383. PDF
• H. Nakahara, T. Sasao and M. Matsuura, "A fast logic simulator using an LUT cascade emulator," ASPDAC 2006, Yokohama Jan. 2006, pp.466-472. PDF
• H. Qin, T. Sasao, and J. T. Butler, " Implementation of LPM address generator on FPGAs," International Workshop on Applied Reconfigurable Computing (ARC2006) Delft, the Netherlands, March 1-3, 2006. Also appeared in Lecture Notes in Computer Science 3985, pp.170-181. PDF
• H. Qin, T. Sasao and Y. Iguchi, "A design of AES encryption circuit with 128-bit keys using look-up table ring on FPGA," IEICE Trans. on Information and Systems, Vol.E89-D, No.3, March 2006, pp.1139-1147. PDF
• H. Qin and T. Sasao, " Design of address generators using multiple LUT cascade on FPGA," SASIMI Workshop, April 2006, Nagoya, Japan, pp.146-152. PDF
• K. Nakamura, T. Sasao, M. Matsuura, K. Tanaka, K. Yoshizumi, H. Nakahara and Y. Iguchi, "A memory-based programmable logic device using look-up table cascade with synchronous static random access memories," Japanese Journal of Applied Physics, Vol. 45, No. 4B, 2006, pp. 3295-3300. April, 2006. PDF
• T. Sasao, "Analysis and synthesis of weighted-sum functions," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 25, No. 5, May 2006, pp. 789 - 796. PDF
• T. Sasao and J. T. Butler, "Implementation of multiple-valued CAM functions by LUT cascades," ISMVL-2006, Singapore, May 17-20, 2006. PDF
• T. Sasao and S. Nagayama, "Representations of elementary functions using binary moment diagrams," ISMVL-2006, Singapore, May 17-20, 2006. PDF
• Y. Iguchi, T. Sasao, and M. Matsuura, "On designs of radix converters using arithmetic decompositions," ISMVL-2006, Singapore, May 17-20, 2006. PDF
• T. Sasao, "Design methods for multiple-valued input address generators," ISMVL-2006(invited paper), Singapore, May 17-20, 2006. PDF
• T. Sasao, "A Design method of address generators using hash memories," IWLS-2006, Vail, Colorado, U.S.A, June 7-9, 2006, pp.102-109. PDF
• H. Nakahara and T. Sasao, "A soft error tolerant LUT cascade emulator," The Fifteenth Asian Test Symposium, (ATS-2006), Nov. 20-23, 2006, pp.115-121, Fukuoka, JAPAN. PDF
• H. Nakahara and T. Sasao, "A PC-based logic simulator using a look-up table cascade emulator," IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, Vol. E89-A, No.12, Dec. 2006, pp.3471-3481, Special Section on VLSI Design and CAD Algorithms. PDF
• D. Debnath and T. Sasao, "Efficient computation of canonical form under variable permutation and negation for Boolean matching in large libraries," IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, Vol. E89-A, No.12, Dec. 2006, pp.3443-3450, Special Section on VLSI Design and CAD Algorithms. PDF
• S. Nagayama, T. Sasao, and J. T. Butler "Compact numerical function generators based on quadratic approximation: architecture and synthesis method," IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, Vol. E89-A, No.12, Dec. 2006, pp.3510-3518,Special Section on VLSI Design and CAD Algorithms. PDF