Publication 2007

• S. Nagayama, T. Sasao, and J. T. Butler, "Numerical function generators using edge-valued binary decision diagrams," ASPDAC-2007,Yokohama, Jan. 25, 2007, pp.535-540. PDF
• H. Nakahara, T. Sasao and M. Matsuura, "A CAM emulator using look-up table cascades," 14th Reconfigurable Architectures Workshop RAW 2007, March 2007, Long Beach California, USA. CD-ROM RAW-9-paper-2, PDF
• D. Debnath and T. Sasao, "A new equivalence relation of logic functions and its application in the design of AND-OR-EXOR networks," IEICE Transaction, Special Section of Discrete Mathematics and Its Applications, Vol.E90-A. No.5, May 2007, pp.932-940. PDF
• T. Sasao, S. Nagayama and J. T. Butler, "Numerical function generators using LUT cascades," IEEE Transactions on Computers, Vol.56, No.6, June 2007, pp.826-838. PDF
• S. Nagayama and T. Sasao, "Representations of elementary functions using edge-valued MDDs," ISMVL-2007, Oslo, Norway, May 13-16, 2007.(CD-ROM) PDF
• Y. Iguchi, T. Sasao, and M. Matsuura, "On designs of radix converters using arithmetic decompositions," ISMVL-2007, Oslo, Norway, May 13-16, 2007.(CD-ROM) PDF
• T. Sasao, "An Application of 16-Valued logic to design of reconfigurable logic arrays," ISMVL-2007, Oslo, Norway, May 13-16, 2007.(CD-ROM) PDF
• T. Sasao and J.T. Butler, "The eigenfunction of the Reed-Muller transformation," RM-2007, Oslo, Norway, May 16, 2007. PDF
• T. Sasao, "Sum-of-generalized products expressions: Applications and minimization," IWLS-2007, San Diego, California, U.S.A, May 30-June 1, 2007, pp.372-379. PDF
• Y. Iguchi, T. Sasao, and M. Matsuura, "Design methods of radix converters using arithmetic decompositions," IEICE Trans. on Information and Systems, Vol.E90-D, No.6, June 2007, pp.905-914. PDF
• H. Qin, T. Sasao, and J. T. Butler, "On the design of LPM address generators using multiple LUT Cascades on FPGAs," International Journal of Electronics, Vol. 94, Issue 5, May 2007, pp.451-467, PDF
• T. Sasao and M. Matsuura, "An implementation of an address generator using hash memories," DSD 2007, 10th EUROMICRO Conference on Digital System Design, Architectures, Methods and Tools, Aug. 27 - 31, 2007, Lubeck, Germany, pp.69-76. PDF
• S. Nagayama, T. Sasao, and J. T. Butler, "Design method of numerical function generators based on polynomial approximation for FPGA implementation," DSD 2007, 10th EUROMICRO Conference on Digital System Design, Architectures, Methods and Tools, Aug. 27 - 31, 2007, Lubeck, Germany, pp. 280-287. PDF
• H. Nakahara, T. Sasao, and M. Matsuura, " A hybrid logic simulator using LUT cascade emulators," The 14th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI 2007), Sapporo, Japan, Oct 15-16, 2007, pp.135-141. PDF
• Y. Iguchi, T. Sasao, and M. Matsuura, "Design methods for binary to decimal converters using arithmetic decompositions," Journal of Multiple-Valued Logic, Vol.13, No.4-6, 2007, pp.503-520. PDF
• M. Matsuura and T. Sasao, "BDD representation for incompletely specified multiple-output logic functions and its application to the design of LUT cascades," IEICE Transaction on Fundamentals of Electronics, Communications and Computer Sciences, Vol.E90-A, No.12, Dec. 2007, pp.2762-2769. PDF
• S. Nagayama, T. Sasao, and J. T. Butler, "Design method for numerical function generators using recursive segmentation and EVBDDs," IEICE Transaction on Fundamentals of Electronics, Communications and Computer Sciences, Vol.E90-A, No.12, Dec. 2007, pp.2752-2761. PDF
• T. Sasao and H. Nakahara, "Implementations of reconfigurable logic arrays on FPGAs," International Conference on Field-Programmable Technology 2007 (ICFPT'07) , Dec. 12-14, 2007, Kitakyushu, Japan, pp.217-223. PDF