Publication 2014

• S. Nagayama, T. Sasao and J. T. Butler, "EVMDD-Based analysis and diagnosis methods of multi-state systems with multi-state components," Journal of Multiple-Valued Logic and Soft Computing, Vol. 22, No.1-2, pp.59-78, 2014. PDF
• S. Nagayama, T. Sasao, and J. T. Butler, "Piecewise arithmetic expressions of numeric functions and their application to design of numeric function generators," Journal of Multiple-Valued Logic and Soft Computing, Vol. 23, No.3-4, pp.293-313, 2014 PDF
• T. Sasao, "Index generation functions: Tutorial," Journal of Multiple-Valued Logic and Soft Computing, Vol. 23, No.3-4, pp.235-263, 2014. PDF
• H. Nakahara, T. Sasao, M. Matsuura, "A heterogeneous multi-valued decision diagram machine for encoded characteristic function for non-zero outputs," Journal of Multiple-Valued Logic and Soft Computing, Vol. 23, No.3-4, pp.365-377, 2014. PDF
• H. Nakahara,T. Sasao and M. Matsuura, "An update method for a CAM emulator using an LUT cascade based on an EVMDD(k)," International Symposium on Multiple-Valued Logic (ISMVL-2014), Bremen, Germany, May 19-22, 2014, pp.1-6. PDF
• T. Sasao, Y. Urano and Y. Iguchi, "A lower bound on the number of variables to represent incompletely specified index generation functions," International Symposium on Multiple-Valued Logic (ISMVL-2014), Bremen, Germany, May 19-22, 2014, pp.7-12. PDF
• S. Nagayama, T. Sasao, J.T. Butler, M. A. Thornton, and T. W. Manikas, "Analysis methods of multi-state systems partially having dependent components using multiple-valued decision diagrams , International Symposium on Multiple-Valued Logic (ISMVL-2014), Bremen, Germany, May 19-22, 2014, pp.190-195. PDF
• D. K. Das, D.Chowdhury, B. B. Bhattacharya and T. Sasao "Inadmissible class of Boolean functions under stuck-at faults," International Symposium on Multiple-Valued Logic (ISMVL-2014), Bremen, Germany, May 19-22, 2014, pp.237-242. PDF
• T. Sasao,"On the average number of variables to represent incompletely specified index generation function," International Workshop on Logic and Synthesis, (IWLS-2014), May 30-June 1, San Francisco, CA. 2014. PDF
• H. Nakahara, T. Sasao and M. Matsuura, "A packet classifier based on prefetching EVMDD(k) machines," IEICE Transactions on Information and Systems, (Special Sections on "Multiple-Valued Logic and VLSI Computing") Vol.E97-D, No.9, pp.2243-2252. PDF
• S. Nagayama, T. Sasao, J. T. Butler, M. A. Thornton, and T. W. Manikas, "On Optimizations of Edge-Valued MDDs for Fast Analysis of Multi-State Systems IEICE Transactions on Information and Systems, (Special Sections on "Multiple-Valued Logic and VLSI Computing") Vol.E97-D, No.9, pp.2234-2242. PDF
• I. Syafalni and T. Sasao, "Head-tail expressions for interval functions," IEICE Transactions on Fundamentals of Electronics, Communication and Computer Sciences, Vol.E97-A,No.10, Oct. 2014, pp.2043-2054. PDF
• I. Syafalni and T. Sasao, Xiaoqing Wen, S. Holst and, K. Miyase, "Soft-error tolerant TCAMs for high-reliability packet classifications," 2014 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), Ishigaki, Japan, pp.471-474, Nov. 17-22, 2014. PDF
• T. Sasao, Y. Urano, and Y. Iguchi, "A Method to find linear decompositions for incompletely specified index generation functions using difference matrix," IEICE Transactions on Fundamentals of Electronics, Communication and Computer Sciences,Vol.E97-A, No.12, Dec.2014, pp.2427-2433. PDF
• J. T. Butler and T. Sasao, "High-speed hardware partition generator," ACM Transactions on Reconfigurable Technology and Systems, Vol.7, No 4, Dec. 2014. PDF
• T. Sasao and J. T. Butler, Applications of Zero-Suppressed Decision Diagrams, Synthesis Lectures on Digital Circuits and Systems, November 2014, 123 pages, Morgan-Claypool. book