2001

- T. Sasao and J. T. Butler, "On the minimization of SOPs for bi-decomposable functions, " Asia and South Pacific Design Automation Conference (ASP-DAC'2001), Jan. 30-Feb. 2, 2001, Yokohama, Japan, pp.219-224. PDF
- T. Sasao,"Compact SOP representations for multiple-output functions: An encoding method using multiple-valued logic," 31th International Symposium on Multiple-Valued Logic, Warsaw, Poland, May 22-24, 2001, pp.207-212. PDF
- T. Sasao, M. Matsuura, and Y. Iguchi, "A cascade realization of multiple-output function for reconfigurable hardware," International Workshop on Logic and Synthesis (IWLS01), Lake Tahoe, CA, June 12-15, 2001. pp.225-230. PDF
- M. Matsuura and T. Sasao, "Representation of incompletely specified switching functions using pseudo-Kronecker decision diagrams," International Workshop on Applications of the Reed Muller Expansion in Circuit Design (Reed-Muller 2001), Starkville, Mississippi, U.S.A, August 10-11, 2001, pp. pp.27-33. PDF
- Y. Iguchi, T. Sasao, and M. Matsuura , "Realization of multiple-output functions by reconfigurable cascades, " International Conference on Computer Design :VLSI in Computers & Processors (ICCD-2001), Austin, TX, Sept. 23-26, 2001. pp. 388-393. PDF
- T. Sasao and J. T. Butler, "Worst and best irredundant sum-of-products expressions, " IEEE Transactions on Computers, Vol. 50, No. 9, Sept. 2001, pp. 935-948.PDF
- R.S. Stankovic and T. Sasao, "A discussion on the history of research in arithmetic and Reed-Muller expressions," IEEE Transactions on CAD, Vol. 20, No.9, Sept. 2001, pp. 1177-1179. PDF
- M. Matsuura and T. Sasao, J.T. Butler, and Y. Iguchi, "Bi-partition of shared binary decision diagrams," Workshop on Synthesis And System Integration of MIxed Technologies (SASIMI-2001), Nara, Japan, Oct. 18-19, 2001, pp.172-177.. PDF
- T. Sasao, M. Matsuura, Y. Iguchi, and S. Nagayama, "Compact BDD representations for multiple-output functions and their applications to embedded system," IFIP VLSI-SOC'01, Montpellier, France, December 3-5, 2001, pp. 406-411. PDF
- S. Hassoun and T. Sasao (eds.), Logic Synthesis and Verification, Kluwer Publishers, (2001-10). Outline

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