Elementary Logic Design (April 2000)
Logic functions and their representation (61 slides: 50 minutes)
  • Logic elements and logic symbols
  • Boolean algebra and logic function
  • Sum-of-products expression and product-of-sums expression
  • Shannon expansion
  • Reed-Muller canonical expression
  • Multilevel logic network
  • Analysis of combinational logic networks
  • Exercises
Optimization of two-level logic networks (57 slide: 50 minutes)
  • Sum-of-products expression and product-of-sums expression
  • Hyper cube
  • Karnaugh map
  • Prime implicant, minimal sum-of-products expression
  • Simplification using Karnaugh maps
  • Applications of minimum sum-of-products expressions
  • Simplification of multiple-output functions
  • Exercises
Synchronous sequential circuits (74 slides: 50 minutes)
  • Introduction to sequential networks
  • Flip-flops
  • Realization of sequential networks
  • State assignment
  • Exercises
Design of an automatic vending machine (39 slides: 30 minutes)
  • Specification of automatic vending machine
  • State diagram/ state table
  • Using SR flip-flops
  • Using D flip-flops
  • Exercises
Analysis of sequential networks (17 slides: 8 minutes)
  • Exercises
Functional circuit (76 slides: 60 minutes)
  • Principle of addition
  • Half adder and full adder
  • Adder
  • Eecoder and encoder
  • Multiplexer and de-multiplexer
  • Shift register
  • Exercises
Transient analysis of combinational logic networks (21 slides: 15 minutes)
  • Delay
  • Hazard
  • Elimination of hazards
  • Exercises
Answers to the exercises (83 Slides 70 minutes)
  • Analysis of contact networks
  • Proof of equivalence of logical expressions
  • Analysis of combinational networks
  • Proof on Boole equations
  • Derivation of minimum sum-of-products expressions
  • Derivation of all the prime implicants
  • Minimization of expressions using don't cares
  • Realization of AND-OR/OR-AND two-level networks
  • State diagram of a counter
  • Design of a counter
  • Design of an automatic vending machine using JKFF
  • Analysis of sequential networks
  • Realization of full adder
  • Synthesis of multiplexer
  • Synthesis of de-multiplexer
  • Synthesis of subtractor
  • Elimination of hazards