edited by Tsutomu Sasao

Kluwer Academic Publishers,

Jan. 1993.

Two-Level Minimization 1. A New Exact and Heuristic Minimizer for Two-level Logic Synthesis Robert K. Brayton, Patrick C. McGeer and Jagesh Sanghavi (University of California, Berkeley) 2. A new Graph Based Implicit Prime and Essential Prime Computation Technique Oliver R. Coudert and Jean. C. Madre (Bull Corporate Research Center) Multi-Level Logic Minimization 3. Logic Synthesizer, the Transduction Method and its Extension, SYLON Saburo Muroga (University of Illinois) 4. Network Optimization using Don't-Cares and Boolean Relations Kuang-Chien Chen (Fujitsu America Inc.) 5. Multi-level Logic Minimization of Large Combinational Circuits by Partitioning Masahiro Fujita, Yusuke Matsunaga, Yutaka Tamiya (Fujitsu Laboratories LTD.) and Kuang-Chien Chen (Fujitsu America Inc.) 6. Area Optimization for Large Circuits by Partial Collapsing Yuichi Nakamura, Kazutoshi Wakabayashi and Tomoyuki Fujita (NEC Corporation) BDD application 7. A New Algorithm for 0-1 Programming Based on Binary Decision Diagrams Seh-Woong Jeong and Fabio Somenzi (University of Colorado) Delay Optimization 8. Delay Models and Sensitization Criteria in the False Path Problem Patrick C. McGeer, Alexander Saldanha, Paul R. Stephan, R. K. Brayton, and Albert L. Sangiovanni-Vincentelli (University of California, Berkeley) Asynchronous circuits. 9. Challenges to Dependable Asynchronous Processor Design Takashi Nanya (Tokyo Institute of Technology) Spectral methods 10. Some Recent Developments in Spectral Logic Design D Varma and E. A. Trachtenberg (Drexel University) FPGA Design 11. FPGA Design by Generalized Functional Decomposition Tsutomu Sasao (Kyushu Institute of Technology) EXOR Logic Synthesis 12. Logic Synthesis using EXOR logic gates Tsutomu Sasao (Kyushu Institute of Technology) 13. AND-EXOR expressions and their Optimization Tsutomu Sasao (Kyushu Institute of Technology) 14. An Efficient Algorithm for Generating Mixed-Polarity Reed-Muller Expansions using Shared Binary Decision Diagrams Koichi Yasuoka (Kyoto University) Technology Mapping 15. A new Technology Mapping Method Based on Concurrent Factorization and Mapping Minoru Inamori and Atsushi Takahara (NTT LSI Laboratories) 16. Logic Gate Sizing in Cell Based Designs Wei-Po Lee and Youn-Long Lin (Tsing Hua University, Taiwan)

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