ISMVL-97 ADVANCE PROGRAM
May 27
1800-2000 Reception and Registration
Faculty Lounge (6th floor of Nicholson Hall) at St. F. X.
May 28
0800-0900 Registration
(All technical sessions will be at the Best Western Claymore Inn.)
0900-0915 Opening Remarks (Chisholm Room)
0915-1015 Session 1: Invited Address (Chisholm Room)
Recent Developments in DNA-Computing,
D. Roo=DF , Institut f=FCr Informatik, University of W=FCrzburg,
Germany
1015-1045 Break
1045-1215 Session 2a: Decomposition (Chisholm Room)
Decomposition of Multiple-Valued Relations,
M. Perkowski, M. Marek-Sadowska, L. Jozwiak, T. Luba, S.
Grygiel, M. Nowicka, R. Malvi, Z. Wang and S. Zhang
Finding Composition Trees for Multiple-Valued Functions,
E. Dubrova , J. C. Muzio and B. von Stengel
Functional Decomposition of MVL Functions, C. Files ,
R. Drechsler and M. A. Perkowski
1045-1215 Session 2b: Technology (Cameron Room)
Application of Resonant-Tunneling Quaternary Quantizer to
Ultrahigh-Speed
A/D Converter,
T. Waho, and M. Yamamoto
Multiple-Junction Surface Tunnel Transistors for Multiple-valued Logic
Circuits,
T. Baba and T. Uemura
Enzyme Transistor Circuits for Bioolecular Computing,
M. Hiratsuka, T. Aoki and T. Higuchi
1215-1330 Lunch & Executive Subcommittee Meeting
1330-1500 Session 3a: Minimization I (Chisholm Room)
Comparison of the Worst and Best Sum-of-Products Expressions for
Multiple-Valued Functions,
J. T. Butler and T. Sasao
Fast Algorithm for Minimizing Reed-Muller Expansions of Systems of
Incompletely Specified MVL Functions,
A.D. Zakrevskij and L.A. Zakrevski
Fast Exact Minimization of Fixed-Polarity Multi-Valued Linear Functions,
R. Drechsler , M. Keim and B. Becker
1330-1500 Session 3b: Algebra (Cameron Room)
Completeness Criteria in Set Logic Under Compositions with Union and
Intersection,
I. Stojmenovic , A. Ngom, C. Reischer and D. A. Simovici
Hyperclones on a Finite Set,
B. Romov
Set-Valued Functions and Regularity,
N. Takagi, Y. Nakamura and K. Nakashima
1500-1530 Break
1530-1630 Session 4a: Minimization II (Chisholm Room)
Multiple-Valued Logic Minimization by Genetic Algorithms,
Y. Hata, K. Hayase and T. Hozumi
Multiple-Valued Product-of-Sums Expression with Truncated Sum,
Y. Hata, N. Kamiura and K. Yamato
1530-1630 Session 4b: Philosophical Aspects (Cameron Room)
Representation of uncertain belief using interval probability,
P. H. Giang
What is Many-Valued Logic?
J.-Y. B=E9ziau
1630-1730 Session 5a: Spectral Techniques (Chisholm Room)
Family of Complex Hadamard Transforms: Relationship with Other
Transforms
and Complex Composite Spectra,
S. Rahardja and B. J. Falkowski
Properties and Applications of Unified Complex Hadamard Transforms,
B. J. Falkowski and S. Rahardja
1630-1730 Session 5b: Testing and Fault Simulation (Cameron Room)
Test Pattern Generation for Combinational Multi-Valued Networks Based
on Generalized D-Algorithm,
V. Shmerko, S. Yanushkevich and V. Levashenko
Fault Simulation in Sequential Multi-Valued Logic Networks,
R. Drechsler , M. Keim and B. Becker
May 29
0900-1000 Session 5: Invited Address (Chisholm Room)
Manyvaluedness and Uncertainty
E. Orlowska, Institute of Telecommunications, Warsaw, Poland
1000-1030 Break
1030-1200 Session 6a: Circuit Applications (Chisholm Room)
Multiple-Valued Programmable Logic Arrays with Universal Literals,
T. Utsumi, N. Kamiura, Y. Hata and K. Yamato
LSI design of a quaternary multiplier with direct generation of partial
products,
O. Ishizuka, A. Ohta, Dwi Handoko, K. Tanno and Z. Tang
One-Transistor-Cell 4-Valued Universal-Literal CAM for Cellular Logic
Image Processing,
T. Hanyu, M. Aragaki and M. Kameyama
1030-1200 Session 6b: Fuzzy Logic (Cameron Room)
On the Mutual Definability of Classes of Generalized Fuzzy Implications
and of Classes of Generalized Negations and S-Norms,
H. Thiele
On Training Fuzzy Logic Based Software Components,
J. Chen and D. C. Rine
Properties of Fuzzy and a-driven Lindenmayer Languages,
E. Meyer zu Bexten and C. Moraga
1200-1330 Lunch & Symposium Subcommittee Meeting
1330-1500 Session 7a: Circuits (Chisholm Room)
A Useful Application of CMOS Ternary Logic to the Realisation of
Asynchronous Circuits,
R. Mariani, R. Roncella, R. Saletti and P. Terreni
Design of Ternary CCD Circuits Referencing to Current-Mode CMOS
Circuits,
X. Wu and M. Pedram
Quaternary Dynamic Differential Logic with Application to Fuzzy-Logic
Circuits,
A. Herrfeld and S. Hentschke
1330-1500 Session 7b: Applications (Cameron Room)
A Proof Method for the Six-Valued Logic for Incomplete Information,
Seiki Akama
Multiple-Valued Logic as a Programming Language,
R.J. Bignall and M. Spinks
Multiple-Valued Immune Network Model and Its Simulations,
Z. Tang, T. Yamaguchi, K. Tashima, O. Ishizuka and K. Tanno
1500-1515 Break
1515-1600 Plenary Session (Chisholm Room)
Evening Banquet
May 30
0900-1000 Session 8: Invited Address (Chisholm Room)
Ternary Decision Diagrams: Survey
T. Sasao, Department of Computer Science and Electronics,
Kyushu Institute of Technology, Japan
1000-1030 Break
1030-1200 Session 9a: Logic Design (Chisholm Room)
On The Synthesis of MVL Functions Using Input and Output Assignments,
M. Abd-El-Barr, G. A. Hamid and M. N. Hasan
Mixed Discrete Optimization of Multiple-Valued Systems,
A. Etzel
Design of an Asynchronous Digital Sytem with B-ternary Logic,
Y. Nagata and M. Mukaidono
1030-1200 Session 9b: Function Representation (Cameron Room)
Circuit Design from Galois Field Decision Diagrams for Multiple-Valued
Functions,
R. Stankovic and R. Drechsler
Fourier Decision Diagrams on Finite Non-Abelian Groups with
Preprocessing,
R. Stankovic
Cube Diagram Bundles: A New Representation of Strongly Unspecified
Multiple-Valued Functions and Relations,
S. Grygiel, M. Perkowski, M. Marek-Sadowska, T. Luba and L. Jozwiak
1200-1215 Closing Remarks (Chisholm Room)