Monday, May 22
1995 Workshop on Post-Binary Ultra-Large Scale Integration
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14:00
Introduction: T. Sasao (5 minutes)
14:05
Session I: Novel Computation, Organizer, J. Mills
Title: Thermodynamics of Computation and Complexity,
Speaker: Jonathan Mills
14:30
Title: Information Theory of Lukasiewicz Logic Arrays
Speaker: Robert Montante
14:55
Break (15 minutes)
Session II: Logic Design, Organizer, T. Sasao
15:10
Title : Ordered Kronecker Function Decision Diagrams.
Speaker: Rolf Drechsler
15:35
Title : On a design of AND-OR-EXOR logic circuits.
Speaker: Tsutomu Sasao
16:00
Title : Design of High Performance Digital System Based on Linearity
Speaker: Michitaka Kameyama
16:25
1800-2000 ISMVL'95 On-Site Registration (continues on Tuesday)
1900-2100 Reception, Musical Arts Center
==============================================================================
Tuesday, May 23
IEEE 25th International Symposium on Multiple-Valued Logic
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0800-0815 Opening Remarks
0815-0915 Invited Address: Gaggle Theory and Multiple-Valued Logic. M.
Dunn, Indiana University
0915-0945 Refreshment break
0945-1125
VLSI
----
Title : A High Speed Interconnect Network using ternary logic
Author : Jens Kargaard Madsen and Stephen I Long
Title : Wire-Free Computing Circuits Using Optical Wave-Casting
Authors: Satoshi Sakurai, Takafumi Aoki and Tatsuo Higuchi
Title : Redundant Complex Number Systems
Authors: Yuji Ohi, Takafumi Aoki and Tatsuo Higuchi
Title : Design of Highly Parallel Multiple-Valued Linear
Digital System for k-Ary Operations Based on
Extended Representation Matrices
Authors: Morihiro Ryu and Michitaka Kameyama
LOGIC DESIGN 1
--------------
Title : Planar Multiple-Valued Decision Diagrams
Authors: Tsutomu Sasao and Jon T. Butler
Title : Reed-Muller Transform for Incompletely
Specified Functions via Sparse Polynomial Interpolation
Authors: Zeljko Zilic and Zvonko Vranesic
Title : Properties of the Zhang-Watari Transform
Authors: Ralph Oenning, Claudio Moraga
1125-1400 Lunch
1400-1515
CIRCUIT DESIGN 1
----------------
Title : Memory Circuits for Multiple Valued Logic Voltage Signals
Author : K. Wayne Current
Title : From Multivalued Current Mode CMOS Circuits to
Efficient Voltage Mode CMOS Arithmetic Operators
Author : K. Navi, D. Etiemble,
Title : Multiple-Valued Arithmetic Integrated Circuits Based on 1.5V-Supply
Dual-Rail Source-Coupled Logic
Authors: Takahiro Hanyu, Akira Mochizuki and Michitaka Kameyama
ALGEBRA 1
---------
Title : The Radii of Sheffer Functions Over E(3)
Authors: Jeffrey Beckman and T.C. Wesselkamper
Title : Classification of Functions and Enumeration of Bases
of Set Logic Under Boolean Compositions
Authors: Alioune Ngom, Corina Reischer and Ivan Stojmenovic
Title : Completeness Theory for Vector Partial Multiple-Valued Logic
Functions
Author : Boris A. Romov
1515-1530 Refreshment Break
1530-1645
DEVICE-BASED CIRCUIT AND TESTING 1
----------------------------------
Title : Quantum Device Model Based Super Pass Gate for Multiple-Valued
Digital
Systems
Authors: Xiaowei Deng, Takahiro Hanyu and Michitaka Kameyama
Title : Random Pattern, Fault Simulation in Multi-Valued Circuits
Authors: Rolf Drechsler, Rolf Krieger, Bernd Becker
Title : The Evaluation of Full Sensitivity for Test Generation in MVL
Circuits
Authors: Elena Dubrova, Dilian Gurov and Jon C. Muzio
LOGIC 1
-------
Title : Paraconsistent Circumscription
Author : Zuoquan Lin
Title : Novel Quantized Transform for Ternary Systems
Authors: Bogdan J. Falkowski and Susanto Rahardja
Title : A Three-Valued Semantics for Discourse Representations
Authors: Seiki Akama and Yotaro Nakayama
=========================
Wednesday, May 24
0800-0815 Opening Remarks
0815-0915 Invited Address:
Resonant Tunneling Transistor and Its Application
to Multiple-Valued Logic Circuits
Takao Waho, NTT LSI Laboratories, NTT, Japan
0915-0945 Refreshment break
0945-1100
FUZZY LOGIC
-----------
Title : On mathematical foundations of fuzzy cluster analysis
Author : Helmut Thiele
Title : On the lattice-isomorphism between fuzzy equivalence relations and
fuzzy partitions
Author : Norbert Schmechel
Title : Segment Matrix Vector Quantization and Fuzzy Logic for Isolated-World
Speech Recognition
Authors: Liusheng Liu, Zhijian Li and Bingxue Shi
LOGIC DESIGN 2
--------------
Title : Efficient Algorithm for the Generation of Fixed Polarity Quaternary
Reed-Muller Expansions
Authors: Bogdan J. Falkowski and Susanto Rahardja
Title : Factorization of Multi-Valued Logic Functions
Authors: Hui Ming Wang, Chung Len Lee and Jwu E Chen
Title : On Input Permutation Technique for Multiple-Valued Logic Synthesis
Authors: Yutaka Hata and Kazuharu Yamato
1100-1400 Lunch
1400-1510
DEVICE-BASED CIRCUIT AND TESTING 2
--------------------
Title : High Speed 3-Valued Logic Gates Based on the
Multiple beta Transistors
Authors: Wang Shoujue, Wu Xunwei and Feng Hongjuan
Title : Fuzzy Membership Function Circuit Using Hysteretic Resonant Tunneling
Diodes
Authors: Hao Tang, Hung Chang Lin
Title : On Designing of 4-Valued Memory With Double-Gate TFT
Authors: Chung Len Lee, Horng Nan Chern, Min Shung Liao and Hui Min Wang
ALGEBRA 2
--------
Title : Join-Irreducible Clones of Multiple Valued Logic Algebra
Authors: Akihiro Nozaki and Grant Pogosyan
Title : Finitary Approximations and Metric Structure of the Space of Clones
Authors: Hajime Machida
Title : Partial Clones containing all permutations
Authors: Lucien Haddad and Ivo G. Rosenberg
Title : Finite Algebraic Models for Residuated Logic
Author : Wendy MacCaull
1515-1530 Refreshment Break
1530-1645
CIRCUIT DESIGN 2
--------------
Title : Multiple-Valued Logic Function Realization
Authors: A.K. Jain, M.H. Abd-El-Barr, and Ronald J. Bolton
Title : Race-Hazard and Skip-Hazard in Multivalued
Combinational Circuits
Authors: Xunwei Wu, Xiexiong Chen and Jizhong Shen
Title : 2^k-ary Cyclic AN Codes for Burst Error Correction
Authors: Ryutaro Murakami, Yoshiteru Ohkura and Ryosaku Shimada
LOGIC 2
-----------------
Title : A Characterization of Kleenean Functions
Authors: Noboru Takagi, Hiroaki Kikuchi, Kyoichi Nakashima and Masao Mukaidono
Title : Uniqueness of Partially Specified Multiple-Valued Kleenean Function
Authors: Hiroaki Kikuchi, Noboru Takagi, Shohachiro Nakanishi and Masao
Mukaidono
Title : On Tableaux for Logic of Paradox
Authors: Zuoquan Lin and Wei Li
1645-1700 Refreshment Break
1700-1800 Plenary session: MVL-TC Meeting
1900-2100 Banquet with entertainment by IU Jazz and Blues Quartet
==============================
Thursday, May 25
0815-0915 Invited Address:
Decomposition of Multiple-Valued Functions.
Tadesz Luba, Technical University of Warsaw,
Warsaw, Poland.
0915-0945 Refreshment break
0945-1100
ARTIFICIAL INTELLIGENCE
-----------------------
Title : Multiple-Valued Genetic Algorithms
Authors: T.C. Wesselkamper and Joshua Danowitz
Title : Learning Multiple-Valued Logic Networks Based on Back Propagation
Authors: Zheng Tang, Okihiko Ishizuka and Koichi Tanno
Title : Three-Valued Constructive Logic and Logic Programs
Authors: Seiki Akama
LOGIC DESIGN 3
--------------
Title : Functional Decision Diagrams for Multiple-valued functions
Author : Radomir S. Stankovic
Title : Multiple-Valued Logic Design Using Multiple-Valued EXOR
Authors: Takahiro Hozumi, Yutaka Hata and Kazuharu Yamato
1100-1115 Closing remarks