ISMVL94 Preliminary Program:
24th INTERNATIONAL SYMPOSIUM ON MULTIPLE-VALUED LOGIC
May 24-27, 1994
The 57 Park Plaza Hotel, Howard Johnson
200 Stuart Street at Park Plaza
Boston, Massachusetts 02116 U.S.A.
Tel: (617)-482-1800
FAX: (617)-451-2750
PROGRAM
Tuesday, May 24, l994
18:00-19:00 Registration: The 57 Park Plaza Hotel
19:00-21:00 Reception
Wednesday, May 25, 1994
08:00-08:30 Registration
08:30-08:45 Opening Remarks
08:45-09:45 Session 1: Invited Address
AS-20 ``Digital Circuit Verification using Partially-Ordered State
Models,''
Randal E. Bryant, C.-J. H. Seger, Carnegie-Mellon Univ.,
U.S.A. and Univ. of British Columbia, Canada
09:45-10:00 Refreshments Break
10:00-12:05 Session 2a: Circuits I
EA-08 ``CML Current Mode Full Adders for 2.5V Power Supply ''
A. Kazeminejad, K. Navi, and D. Etiemble,
Univ. of Paris Sud, France
AM-23 ``A Current-Mode CMOS Quaternary Multiplier Circuit''
W.-S. Chu and K. W. Current, Univ. of California, Davis, U.S.A.
AS-14 ``Multiple-Valued Current-Mode MOS Integrated Circuits
Using Dual-Rail Source-Coupled Logic''
T. Hanyu, A. Mochizuki, and M. Kameyama, Tohoku Univ., Japan
EA-03 ``Performance of CMOS Current Mode Full Adders''
K. Navi, A. Kazeminejad, D. Etiemble,
Univ. of Paris Sud, France
AS-07 ``Multi-Variable MVL Function Synthesization by Using Hybrid
Mode CMOS Logic''
Y.-J. Chang and C. L. Lee, National Chiao Tung Univ., China
10:00-12:05 Session 2b: Logic Design I
AS-06 ``Algebraic Division for Multilevel Logic Synthesis
of Multi-Valued Logic Circuits'' H. M. Wang, C. L. Lee, and
J. E. Chen, National Chiao Tung Univ. and Chung-Hua
Polytechnic Inst., China,
AS-05 ``A Multiple-Valued Logic Synthesis using the Kleenean
Coefficients'' Y. Hata and K. Yamato, Himeji Inst. of
Technology, Japan
AM-25 ``Decomposition-Based Synthesis of Multiple-Valued
Functions for Threshold Logic Network Realization''
G. H. Abdel-Hamid and M. H. Abd-El-Barr,
King Fahd Univ., Saudi Arabia
EA-05 ``Efficient Graph-based Representation of MV-Functions
with an Application to Genetic Algorithms''
B. Becker and R. Drechsler, Univ of Frankfurt, Germany
AM-06 ``Multiple-Valued Logic Operations with Universal Literals''
G. W. Dueck and J. T. Butler, St. Francis Xavier Univ., Canada,
and Naval Postgraduate School, U.S.A.
12:05-14:00 Lunch and Executive Subcommittee Meeting
14:00-15:15 Session 3a: Logic Design II
AM-20 ``The Calculation of Reed-Muller Coefficients of
Multiple-Valued Functions through Multi-Place Decision
Diagrams'' R. S. Stankovic, M. Stankovic, C. Moraga,
and T. Sasao, Yugoslavia, Univ. of Dortmund, Germany, and
Kyushu Inst. of Technology, Japan
AM-26 ``Spectral Transformation of Multiple-Valued Decision
Diagrams'' D. M. Miller, Univ. of Victoria, Canada
AM-07 ``A Design Method for Look-up Table Type FPGA by
Pseudo-Kronecker Expansion'' T. Sasao and J. T. Butler,
Kyushu Inst. of Technology, Japan, and Naval Postgraduate
School, U.S.A.
14:00-15:15 Session 3b: Logic I
AM-11 ``Lattices of Resolution Logics'' Z. Stachniak,
York Univ., Canada
AM-17 ``Computing Prime Implicants/Implicates for Regular
Logics'' A. Ramesh and N. V. Murray, State Univ. of
New York at Albany, U.S.A.
AS-03 ``Minimization for Kleene-Stone Logic Functions''
N. Takagi, K. Nakashima and M. Mukaidono, Toyama Prefectural
Univ. and Meiji Univ., Japan
15:15-15:30 Refreshments Break
15:30-17:10 Session 4a: Fuzzy Logic, Applications, and Circuits
AM-04 ``Parallel Processing of Fuzzy Inferences''
C. Moraga, J. Canas, R. Monge, L. Salinas, and M. Gomez,
Univ. of Dortmund, Germany, and Univ. Tecnica Federico
Santa Maria, Chile
AM-09 ``On Scheduling in Multiprocessor Systems Using Fuzzy
Logic'' A. S. Kaviani and Z. G. Vranesic, Univ. of Toronto,
Canada
AM-16 ``A Field Programmable Analog Array for Multi-Valued and
Fuzzy Logic Applications'' E. Pierzchala, M. A. Perkowski,
and S. Grygiel, Portland State Univ., U.S.A.
AM-10 ``Multi-Peak Resonant Tunneling Diodes Based Fuzzifier''
H. Tang, H. C. Lin, and S. J. Wei, Univ. of Maryland,
U.S.A.
15:30-17:10 Session 4b: Algebra I
AM-14 ``Enumeration of Functions and Bases of Three-Valued
Set Logic under Compositions with Boolean Functions''
J. Demetrovics, C. Reischer, D. A. Simovici, and
I. Stojmenovic, Hungarian Academy of Science, Hungary,
Univ. of Quebec at Trois-Rivieres, Canada, Univ. of
Massachusetts at Boston, U.S.A., and Univ. of Ottawa,
Canada
AM-05 ``Searching for Complete Functions over E(3) with Small
Radii'' F. J. Cabrasawan and T. C. Wesselkamper,
Hunter College, U.S.A.
AM-08 ``Completeness Criteria in Many-Valued Set Logic Under
Compositions with Boolean Functions'' I. Stojmenovic,
Univ. of Ottawa, Canada
AM-27 ``The Completeness Problem on the Product of Algebras
of Finite-Valued Logic'' B. A. Romov, New York, U.S.A.
Thursday, May 26, 1994
08:30-09:30 Session 5: Invited Address
AM-24 ``Resonant Tunneling Diodes for Multi-Valued
Digital Applications''
Hung Chang Lin, Univ. of Maryland, U.S.A.
09:30-09:45 Refreshments Break
09:45-11:50 Session 6a: Circuits II
AM-19 ``Interband-Tunneling III-V Semiconductor Structures
for Multiple-Valued Literal and Arithmetic Functions''
L. J. Micheel, H. Hartnagel, W. Anderson, S. Kirchoefer,
and N.A. Papanicolaou, Air Force Wright Laboratory, U.S.A.,
Technische Hochschule Darmstadt, Germany, and Naval
Research Laboratory, U.S.A.
AS-11 ``Design of Wave-Parallel Computing Circuits for
Densely connected Architectures'' Y. Yuminaka, T. Aoki,
and T. Higuchi, Tohoku Univ., Japan
AS-17 ``Design of Multiwave Computing Circuits Based on a Model
of Integrated Opto-Electronic Devices'' Y. Watanabe,
T. Aoki, and T. Higuchi, Tohoku Univ., Japan
AS-15 ``Design of Multiple-Valued Linear Digital Circuits
for Highly Parallel K-Ary Operations'' M. Nakajima
and M. Kameyama, Tohoku Univ., Japan
AS-12 ``Design of Multiplex Interconnection Networks for
Massively Parallel Computing Systems'' T. Takimoto,
T. Aoki, and T. Higuchi, Tohoku Univ., Japan
09:45-11:50 Session 6b: Logic II
EA-01 ``Efficient Deduction in Many-valued Logics''
R. Haehnle, Univ. of Karlsruhe, Germany
EA-06 ``The Satisfiability Problem in MV Horn Formulae''
G. Escalada and F. Manya, Centro de Estudios Avanzados
de Blanes, Spain
EA-07 ``Approximating Propositional Calculi by MV Logics''
M. Baaz and R. Zach, Technische Univ. Wien, Austria
EA-10 ``On S-Quantifiers and T-Quantifiers''
H. Thiele, Univ. of Dortmund, Germany
AS-01 ``An Algebraic Method to Decide the Deduction Problem in
Many-valued Propositional Calculus'' J.-Z. Wu and
H.-Y. Tan, Academia Sinica and LanZhou Univ., China
11:50-14:00 Lunch and Symposium Subcommittee Meeting
14:00-15:00 Session 7: Invited Address
EA-00 "Soft Computing Perspectives"
Elie Sanchez, Institut Mediterraneen de Technologie, France
15:00-15:15 Refreshments Break
15:15-16:30 Session 8a: Logic Design III
AM-18 ``Full Sensitivity and Test Generation for
Multiple-Valued Logic Circuits'' E. Dubrova,
D. Gurov, and J. C. Muzio, Univ. of Victoria,
Canada
AS-08 ``Complete Test Set for Multiple-Valued Logic Networks''
H. M. Wang, C. L. Lee, and J. E. Chen, National Chiao Tung
Univ. and Chung-Hua Polytechnic Inst., China
AS-04 ``Design of Fault-Tolerant Cellular Arrays on
Multiple-Valued Logic'' N. Kamiura, Y. Hata, and
K. Yamato, Himeji Inst. of Technology, Japan
15:15-16:30 Session 8b: Algebra II
AS-16 ``Hereditary Clones of Multiple Valued Logic Algebra''
G. Pogosyan, A. Nozaki, and M. Miyakawa, Intl. Christian
Univ., Otsuma Women's Univ., and Tsukuba Coll. of Technology,
Japan
AM-03 ``Many-valued Generalizations of Two Finite Intervals
in Post's Lattice'' G. Denham, Univ. of British Columbia,
Canada
AM-13 ``Several Remarks on Algebraic Entropy'' C. Reischer,
D. A. Simovici, and I. Stojmenovic, Univ. of Quebec at
Trois-Rivieres, Canada, Univ. of Massachusetts at Boston,
U.S.A., and Univ. of Ottawa, Canada
16:30-16:45 Break
16:45-17:45 Plenary Session: Multiple-Valued Logic
Technical Committee Meeting
18:30-21:30 Banquet:
Banquet Address
Harpsicord Recital
Friday, May 27, 1994
09:00-10:40 Session 9a: Logic Design IV
AS-09 ``Identification of Linear Ternary Logic Functions and
its Algorithms'' B. Fei, Q. Hong, and G. Zhang, Ningbo
Univ. and Hangzhou Inst. of Electronics Engineering, China
AM-15 ``Knot Automata'' L. H. Kauffman, Univ. of Illinois at
Chicago, U.S.A.
AM-21 ``Multiple-Valued-Input TANT Networks''
M. Chrzanowska-Jeske and M. A. Perkowski, Portland State
Univ., U.S.A.
AM-02 ``Multiple-valued Combinational Circuits with Feedback''
J. T. Butler and T. Sasao, Naval Postgraduate School,
U.S.A., and Kyushu Inst. of Technology, Japan
09:00-10:15 Session 9b: Logic III
AS-10 ``On Multiple-Valued Separable Unordered Codes''
Y. Nagata and M. Mukaidono, Univ. of the Ryukyus
and Meiji Univ., Japan
AM-01 ``A Weak Propositional Calculus for Signal Processing
with Thresholds'' G. Epstein, Univ. of North Carolina
at Charlotte, U.S.A.
AS-18 ``A Four-Valued Logic and Switch-Level Differences''
M. Hu, Shanghai Inst. of Railway Technology, China
10:40-11:00 Break
11:00-12:00 Lunch
ISMVL94 Registrants are welcome to attend the following
Affiliated Event: 3rd INTERNATIONAL WORKSHOP ON
POST-BINARY ULSI SYSTEMS
Friday, May 27, 1994
The 57 Park Plaza Hotel
Boston, Massachusetts
Sponsor: The Japanese Research Group on Multiple-Valued Logic
Chair: Tsutomu Sasao, Kyushu Inst. of Technology, Japan
12:00-12:10 Introduction: T. Sasao
12:10-13:10 PART I: Systems and Implementation
Organizer: Lutz Micheel, Air Force Wright
Laboratory, U.S.A.
13:10-13:30 Break
13:30-14:30 PART II: Field Programmable Arrays and Systems
Organizer: Marek Perkowski, Portland State
Univ., U.S.A.
14:30-14:50 Break
14:50-15:50 PART III: TBA