Sunday, July 12 
16:00-21:00  Registration (Miyako Hotel)
18:00-19:00  Reception (Only for the participants registered in Logic Synthesis 
                        and Microprocessor Symposium)
Monday, July 13 
10:00-10:20  Welcome
             Shizuo Mukae, President, Kyushu Institute of Technology 
             Sho Yoshida, Dean, Faculty of Computer Science and Systems
             Engineering, Kyushu Institute of Technology  
10:20-12:10  Keynote Address 
             Marvin Minsky (Massachusetts Institute of Technology)
12:10-13:30  Lunch
13:30-13:40  Opening and Introduction
             Tsutomu Sasao (Kyushu Institute of Technology)
13:40-14:20  Session 1: Two-Level Minimization
             Chairperson: Tsutomu Sasao (Kyushu Institute of Technology)
        1.1  A New Exact and Heuristic Minimizer for Two-Level Logic Synthesis
             Robert K. Brayton, Patrick C. McGeer and Jagesh Sanghavi 
             (University of California, Berkeley)
14:20-14:30  Break
14:30-15:00  Session 2: Multi-Level Logic Minimization 
             Chairperson: Robert K. Brayton (University of California, Berkeley)
        2.1  Multi-level Logic Minimization of Large Combinational Circuits
             by Partitioning 
             Masahiro Fujita, Yusuke Matsunaga, Yutaka Tamiya (Fujitsu 
             Laboratories LTD.) and Kuang-Chien Chen (Fujitsu America Inc.)
        2.2  A Vectorized Algorithm for the Transduction Method
             Yuji Kukimoto, Tsutomu Saito and Hidehiko Tanaka 
             (University of Tokyo)
        2.3  Area Optimization for Large Circuits by Partial Collapsing
             Yuichi Nakamura, Kazutoshi Wakabayashi and Tomoyuki Fujita
             (NEC Corporation)
15:00-15:30  Poster/ Break              
15:30-16:10  Session 3: Microprocessor Design
             Chairperson: Takashi Nanya (Tokyo Institute of Technology)
        3.1  Microprocessor Design in the 1990's
             Greg Grohoski (IBM Advanced Workstation Division)
16:10-16:20  Break
16:20-16:50  Session 4: Microprocessor Architecture 
             Chairperson: Itsujiro Arita (Kyushu Institute of Technology)
        4.1  RISC Microprocessor Implementations with Resource Allocation
             Balanced for Instruction Mix
             Manesh Pandey (Carnegie-Mellon University)
             and Akhilesh Tyagi (University of North Carolina)
        4.2  A Vector Microprocessor Architecture
             Kazuaki Murakami, Tetsuo Hironaka, Takashi Hashimoto
             and Hiroto Yasuura (Kyushu University)
        4.3  Microprocessor Architecture Design using High-Level Synthesis
             System
             Akira Nagoya, Yukihiro Nakamura and Ryo Nomura
             (NTT Communication Science Laboratories)
16:50-17:30  Poster 
18:30-20:30  Banquet (Iizuka)

Tuesday, July 14
10:00-10:40  Session 5: Delay Faults
             Chairperson: Hiroto Yasuura (Kyushu University)
       5.1   Identification of Redundant Delay Faults
             Daniel Brand and Vijay S. Iyengar (IBM Research Division)
10:40-10:50  Break
10:50-11:30  Session 6: Delay Computation
             Chairperson:  Daniel Brand (IBM Research Division)
       6.1   Computation of Floating Mode Delay in Combinational Circuits:
             Practice and Implementation.
             Srinivas Devadas (MIT), Kurt Keutzer (Synopsys Inc.),
             Sharad Malik (Princeton University), and Albert Wang 
             (Synopsys Inc.).
11:30-11:50  Session 7: Various Aspects of Logic Synthesis
             Chairperson: Teruhiko Yamada (Meiji University)
       7.1   Delay Models and Sensitization Criteria in the False Path Problem
             Patrick C. McGeer, Alexander Saldanha, Paul R. Stephan, 
             Robert K. Brayton, and Albert L. Sangiovanni-Vincentelli
             (University of California, Berkeley)
       7.2   Design Verification of Asynchronous Sequential Circuits using 
             Symbolic Model Checking
             Kiyoharu Hamaguchi(Kyoto University), Hiromi Hiraishi(Kyoto Sangyo
             University), and Shuzo Yajima (Kyoto University)
11:50-12:20  Poster    
12:20-13:30  Lunch
13:30-14:10  Session 8: Transduction Method
             Chairperson: Tsutomu Sasao (Kyushu Institute of Technology)
             Logic Synthesizers, the Transduction Method and its Extension,
             SYLON
       8.1   Saburo Muroga (University of Illinois)
14:10-14:20  Break 
14:20-14:50  Session 9: Technology Mapping      
             Chairperson: Shin-Ichi Minato (NTT LSI Laboratories)
       9.1   New Technology Mapping Method Based on Concurrent Factorization
             and Mapping
             Minoru Inamori and Atsushi Takahara (NTT LSI Laboratories)
       9.2   Practical Features of FUSION Logic Synthesis System
             Hiroshi Ichiryu, Ko Yoshikawa, Hisato Tanishita and
             Shigenobu Suzuki  (NEC Corporation)
       9.3   Logic Gate Sizing in Cell-Based Designs
             Wei-Po Lee and Youn-Long Lin (Tsing Hua University, Taiwan)
14:50-15:30  Poster /Break
15:30-16:10  Session 10: Prime Implicants Computation
             Chairperson: Masahiro Fujita (Fujitsu Laboratories LTD.) 
      10.1   A new Implicit Graph Based Prime and Essential Prime Computation 
             Technique
             Oliver R. Coudert and Jean C. Madre (Bull Corporate Research
             Center)
16:10        Break 
16:30        Bus leaves for Hakata Station
18:00-20:00  Party for Logic Synthesis Symposium (Hakata Miyako Hotel) 
             Chairperson: Hiroto Yasuura (Kyushu University)
20:00-       Optional walking Tour to Hakata-Gion-Yamakasa Festival

Wednesday, July 15
10:00-10:40  Session 11: Asynchronous Synthesis
             Chairperson:  E.A. Trachtenberg (Drexel University)
       11.1  Challenges to Dependable Asynchronous Processor Design 
             Takashi Nanya (Tokyo Institute of Technology)
10:40-10:50  Break           
10:50-11:30  Session 12: Boolean Relation
             Chairperson: Saburo Muroga (University of Illinois)
       12.1  Network Optimization using Don't-Cares and Boolean Relations
             Kuang-Chien Chen (Fujitsu America Inc.)
11:30-12:00  Session 13:  FPGA Design
             Chairperson: Youn-Long Lin (Tsing Hua University, Taiwan)
       13.1  FPGA Design for Digital Telecommunication Circuits using a High 
             Level Design System
             Kazuhisa Yamada, Hiroshi Nakada, Akihiro Tsutsui, Tatsuya Fujii
             and Naohisa Ohta (NTT Transmission Systems Laboratories)
       13.2  FPGA Design by Generalized Functional Decomposition
             Tsutomu Sasao (Kyushu Institute of Technology)
       13.3  On the Analysis of an FPGA Architecture
             Tsutomu Sasao (Kyushu Institute of Technology) and
             Jon T. Butler (Naval Postgraduate School) 
 12:00-12:30 Poster
 12:30-13:30 Lunch
 13:30-14:10 Session 14: Spectral Logic Design
             Chairperson: Kurt Keutzer (Synopsys Inc.)
       14.1  Some Recent Developments in Spectral Logic Design
             E. A. Trachtenberg (Drexel University)
 14:10-14:20 Break          
 14:20-15:00 Session 15: BDD Application
             Chairperson: Robert K. Brayton (University of California, Berkeley)
       15.1  A New Algorithm for 0-1 Programming Based on Binary
             Decision Diagrams
             Seh-Woong Jeong and Fabio Somenzi (University of Colorado)
 15:00-15:10 Break 
 15:10-15:50 Session 16: EXOR Logic Synthesis
             Chairperson: Jon T. Butler (Naval Postgraduate School) 
       16.1  Efficient Algorithm for Reed-Muller expansions of Completely
             and Incompletely Specified Functions
             Maki K. Habib (University of Technology, Baghdad)
       16.2  An Efficient Algorithm for Generating Mixed-Polarity Reed-Muller
             Expansions using Shared Binary Decision Diagrams
             Koichi Yasuoka (Kyoto University)
       16.3  Optimization of AND-EXOR Expressions using Ternary Decision 
             Diagrams
             Tsutomu Sasao and Takahisa Amada (Kyushu Institute of Technology)
       16.4  A Design Method of AND-OR-EXOR Circuits
             Tsutomu Sasao Takahisa Amada   (Kyushu Institute of Technology)
l5:50-16:30  Poster/ Break
16:30        Bus to Fukuoka Airport and Hakata Station
             Flights to Tokyo, Osaka, Nagoya, and Honolulu.
             Shinkansen-Train to Osaka and Nagoya.