IWLS 2020 Program.

Day 1: Monday, July 27 in Pacific Time (PT)
Day 2: Wednesday, July 29 in Japan Standard Time (JST)
Day 3: Thursday, July 30 in Central European Summer Time (CEST)

July 27
Keynote 1  
Chair: Heinz Riener  
Accelerator Synthesis for Agile Hardware Specialization: A New Dawn  12  
Zhiru Zhang  

Session 1: To SAT solve, or not to SAT solve  
Session Chair: Vinicius Callegaro  
Determining the Multiplicative Complexity of Boolean Functions using SAT  14  
Mathias Soeken  
SAT-based Exact Physical Design for Field-coupled Nanocomputing Technologies  22  
Marcel Walter, Winston Haaswijk, Robert Wille, Frank Sill Torres and Rolf Drechsler  
Simulation-Guided Boolean Resubstitution  30  
Siang-Yun Lee, Heinz Riener, Alan Mishchenko, Robert Brayton and Giovanni De Micheli  
Programming Contest Session  
Moderator: Gai Liu  
Speakers: Alan Mishchenko, Sat Chatterjee, and Gai Liu  

Special Session 1  
Session Chair: Tsung-Yi Ho  
The Challenges of Automating the Design Flow of Superconducting Electronic Circuits  38  
Jamil Kawa, Synopsys  
AQFP Superconducting-based Deep Learning Acceleration  39  
Yanzhi Wang, NEU  
Energy-Efficient Superconductor Digital Circuit Technology for High-Performance  40  
NobuyukiYoshikawa, YNU  

July 29
Keynote 2 
Chair: Luca Amaru Recent Topics and Future Perspectives on BDD/ZDD-Based Discrete Structure 41 Manipulation 
Shin-ichi Minato, Kyoto University 

Session 2: Approximate synthesis and fault equivalence identification 
Session Chair: Jie-Hong Roland Jiang A Low-Cost FSM-based Bit-Stream Generator for Low-Discrepancy Stochastic Computing 42 
Sina Asadi and M. Hassan Najafi 
Exploring Target Function Approximation for Stochastic Circuit Minimization 50 
Chen Wang, Weihua Xiao, John P. Hayes and Weikang Qian 
SAT-Based Sequential Fault Equivalence Identification in Functional Safety Verification 58 
Ai Quoc Dao, Mark Po-Hung Lin and Alan Mishchenko 

Session 3: Optimize your functions: new heuristic and exact methods 
Session Chair: Alan Mishchenko Auto-tuning framework for BDD packages 66 
Yukio Miyasaka and Masahiro Fujita 
Practical Multi-armed Bandits in Boolean Optimization 74 
Cunxi Yu 
Reduction Methods of Variables for Large-Scale Classification Functions 82 
Tsutomu Sasao 

Session 4: Compress and secure your data: Synthesis can help  
Session Chair: Zhufei Chu  
Design Optimization for Faster Fp256 Elliptic Curve Cryptography  88  
Kento Ikeda and Makoto Ikeda  
Lossless compression via two-level logic minimization: a case study using Chess endgame  95  
Dave Gomboc and Christian R. Shelton  

July 30
Keynote 3 
Chair: Pierre-Emmanuel Gaillardon Logic Synthesis for optimizing the performance of SW-based Homomorphic calculations 103 
Olivier Hero, CEA List 

Session 5: XORs are fun! 
Session Chair: Petr Fi.er Symbolic Uniform Sampling with XOR Circuits 104 
Yen-Ting Lin, Jie-Hong R. Jiang and Victor N. Kravets 
Three-Input Gates for Logic Synthesis 112 
Dewmini Sudara Marakkalage, Eleonora Testa, Heinz Riener, Alan Mishchenko, Mathias Soeken and Giovanni De Micheli 
XMG-based Logic Synthesis for Emerging Reconfigurable Nanotechnologies 119 
Shubham Rai, Heinz Riener, Giovanni De Micheli and Akash Kumar 

Updates on the EPFL logic synthesis and ECO benchmarks 
Moderator: Giulia Meuli 

Session 6: Predict and design your critical paths 
Session Chair: Mathias Soeken EaSyOpt: Predicting Post Place and Route Critical Paths for Early Synthesis Optimization 128 
Walter Lau Neto, Matheus Trevisan Moreira, Luca Amaru, Cunxi Yu and Pierre-Emmanuel Gaillardon 
Variation-Tolerant Voltage Over-Scalable Design with Critical Path Isolation and Bit-Width Scaling 136 
Yutaka Masuda, Jun Nagayama, TaiYu Cheng, Tohru Ishihara, Yoichi Momiyama and Masanori Hashimoto