Co-located with the
Design Automation Conference

26th International Workshop
on Logic & Synthesis

June 17 – 18, 2017

Thompson Conference Center — Austin, TX

Austin Area

Our sponsors


IWLS 2017 Preliminary Program

Saturday June 17, 2017

8:50am - 9:00am: Workshop Opening
Jie-Hong Roland Jiang

9:00am - 10:30am: Special Session on Advances in Formal Verification
Programming Constraint Services with Z3
Nikolaj Bjorner (Microsoft)
Industrial Scale Formal Verification Using ACL2 Theorem Prover
Anna Slobodova (Centaur Technology)
Safety across the HW/SW interface - can Formal Methods meet the challenge?
Wolfgang Kunz (University of Kaiserslautern, Germany)

10:30am - 11:00am: Coffee Break

11:00am - 12:30am: Session 1 - Let's Get Warmed Up: Logic Synthesis
Deep Learning for Logic Optimization
Winston Haaswijk, Edo Collins, Benoit Seguin, Mathias Soeken, Sabine Süsstrunk, Frédéric Kaplan and Giovanni De Micheli (EPFL, Switzerland)
Exact Synthesis For Logic Synthesis Applications With Complex Constraints
Eleonora Testa and Mathias Soeken (EPFL, Switzerland), Odysseas Zografos and Francky Catthoor (KU Leuven and IMEC, Belgium) and Giovanni De Micheli (EPFL, Switzerland)
Anubis: A new benchmark for incremental synthesis
Rafael Trapani Possignolo, Nursultan Kabylkas and Jose Renau (University of California, USA)

12:30am - 2:00pm: Lunch

2:00pm - 3:30pm: Session 2 - More Synthesis: Engineering Change Order, Synthetic Biology, Stochastic Computing
Sequential Engineering Change Order under Retiming and Resynthesis
Nian-Ze Lee (National Taiwan University, Taiwan), Victor Kravets (IBM, USA) and Jie-Hong Roland Jiang (National Taiwan University, Taiwan)
Synthesis and Optimization of Recombinase-Based Genetic Circuits
Chun-Ning Lai and Jie-Hong Roland Jiang (National Taiwan University, Taiwan)
Design of Reliable Stochastic Number Generators Using Emerging Devices for Stochastic Computing
Meng Yang and Weikang Qian (Shanghai Jiao Tong University, China)

3:30pm - 5:00pm: Poster Session (including coffee and snacks)
SAT-Based Optimization with Don’t Cares Revisited
Alan Mishchenko, Robert Brayton (University of California Berkeley, USA), Ana Petkovska and Mathias Soeken (EPFL, Switzerland)
On Affine Equivalence of Logic Functions
Tsutomu Sasao and Masato Maeta (Meiji University, Japan)
Cut Generation for Reverse Engineering of GateLevel Netlists
Baruch Sterin (University of California Berkeley, USA), Mathias Soeken, Giovanni De Micheli (EPFL, Switzerland) and Robert Brayton (University of California Berkeley, USA)
Variable Reordering in Binary Decision Diagrams
Chuan Jiang, Junaid Babar, Gianfranco Ciardo, Andrew Miner and Benjamin Smith (Iowa State University, USA)

5:00pm - 5:45pm: IWLS 2017 Programming Contest: "Y Logic Synthesis"
Mathias Soeken
3rd prize: EPFL Team
Winston Haaswijk (EPFL, Switzerland)
2nd prize: NTU Team
Chun-Ning Lai, Kuan-Hua Tu, Nian-Ze Lee, Li-Cheng Chen, and Jie-Hong Roland Jiang (National Taiwan University, NTU, Taiwan)
1st prize: UFRGS Team
Felipe Marranghello, Jody Matos, Gilson Webber, Vinicius Callegaro​, Augusto Neutzling, Andre Reis and Renato Ribas (UFRGS, Brazil)

5:45pm - 6:00pm: Update on the EPFL benchmark best result submissions
Mathias Soeken

6:00pm: Dinner

Sunday June 18, 2017

8:30am - 9:30am: Keynote 1 - DA Perspectives and Futures: An Update
Andrew B. Kahng (UC San Diego, USA)

9:30am - 10:30am: Keynote 2 - Machine Learning in Formal Verification
Manish Pandey (Synopsys, USA)

10:30am - 11:00am: Coffee Break

11:00am - 12:30am: Session 3 - Designer's Best Friends: XAIGs, BDDs, and MAJ
On XAIG Rewriting
Ivo Háleček, Petr Fišer and Jan Schmidt (Czech Technical University in Prague, Czech Republic)
Functional Decomposition Using Majority
Zhufei Chu (Ningbo University, China and EPFL, Switzerland), Mathias Soeken (EPFL, Switzerland), Yinshui Xia (Ningbo University, China) and Giovanni De Micheli (EPFL, Switzerland)
A Divide and Conquer Factoring Algorithm for Read-Once Functions
Vinicius Callegaro, Felipe Marranghello (UFRGS, Brazil), Mayler Martins (Carnegie Mellon University, USA), Renato Ribas, Andre Reis (UFRGS, Brazil) and Marek Perkowski (Portland State University, USA)

12:30am - 2:00pm: Lunch

2:00pm - 3:30pm: Session 4 - Is Everything Correct?: Verification
Property Directed Reachability with Word Level Abstraction
Yen-Sheng Ho, Alan Mishchenko and Robert Brayton (University of California Berkeley, USA)
Enhancing PDR/IC3 with Localization Abstraction
Yen-Sheng Ho, Alan Mishchenko, Robert Brayton (University of California Berkeley, USA) and Niklas Een (Google Inc, USA)
Boolean Grobner Basis Reductions on Datapath Circuits Using the Unate Cube Set Algebra
Utkarsh Gupta, Priyank Kalla and Vikas Rao (University of Utah, USA)

3:30pm - 4:00pm: Coffee Break

4:00pm - 6:00pm: Session 5 - Last, not least: High-level, Compilation, and Mapping
Power-Driven Simultaneous Scheduling and Module Selection in HLS using Global Probability Maps
Xiuyan Zhang and Shantanu Dutt (University of Illinois-Chicago, USA)
Advanced Datapath Synthesis using Graph Isomorphism
Cunxi Yu (University of Massachusetts, USA), Mihir Choudhury, David J. Geiger, Andrew Sullivan (IBM, USA) and Maciej Ciesielski (University of Massachusetts, USA)
SAT-Based Area Recovery in Structural Technology Mapping
Bruno De O. Schmitt (EPFL, Switzerland), Alan Mishchenko and Robert K. Brayton (University of California Berkeley, USA)
A Compiler for Parallel and Resource-Constrained Programmable in-Memory Computing
Giulia Meuli, Mathias Soeken (EPFL, Switzerland), Pierre-Emmanuel Gaillardon (University of Utah, USA) and Giovanni De Micheli (EPFL, Switzerland)

6:00pm - 6:15pm: Closing Remarks