Co-located with the
Design Automation Conference

24th International Workshop
on Logic & Synthesis

June 12 – 13, 2015

Computer History Museum — Mountain View, CA
IWLS 2015 Program

Friday June 12, 2015

8:00am - 8:15am: Welcome Breakfast

8:15am - 8:30am: Workshop Opening
Andre Reis

8:30am - 9:30am: Keynote 1
Session Chair: André Reis
EDA 3.0 [slides]
Leon Stok, IBM

9:30am - 10:30am: Session 1 - Synthesis for Different Technologies
Session Chair: André Reis
A Soft-Error Tolerant TCAM for Multiple-Bit Flips Using Partial Don’t Care Keys
Infall Syafalni (Logic Research Co., Ltd., Japan), Tsutomu Sasao (Meiji University, Japan) and Xiaoqing Wen (Kyushu Institute of Technology, Japan)
Automated Synthesis Approaches for Digital Integrated Design of Spin-Diode Circuits
Mayler Martins, Felipe Marranghello (UFRGS, Brazil), Joseph Friedman (Univ. Paris-Sud, CNRS, France), Alan Sahakian (Northwestern University, USA), Renato Ribas and Andre Reis (UFRGS, Brazil)

10:30am - 11:00am: Break

11:00am - 12:30am: Session 2 - Decomposition of Logic Functions
Session Chair: Tsutomu Sasao
Recursive Decomposition of Sparse Incompletely-Specified Functions
Robert Brayton and Alan Mishchenko (UC Berkeley, USA)
A bottom-up disjoint-support decomposition based on Boolean difference analysis
Vinicius Callegaro, Felipe Marranghello, Mayler Martins, Renato Ribas and Andre Reis (UFRGS, Brazil)
Distributed Environment for Logic Factoring
Victor Kravets (IBM TJ Watson Research Center, USA)

12:30am - 2:00pm: Lunch

2:00pm - 3:00pm: Keynote 2
Session Chair: Dirk Stroobandt
Physical Synthesis 2.0 [slides]
Andrew Kahng, UCSD

3:00pm - 4:00pm: Session 3 - Physical Synthesis
Session Chair: Dirk Stroobandt
Placed AIGs as a Logical-Physical Data-Structure for VLSI Circuit Design
Jody Maick Matos and Andre Reis (UFRGS, Brazil)
The EPFL Combinational Benchmark Suite
Luca Amaru, Pierre-Emmanuel Gaillardon and Giovanni De Micheli (EPFL, Switzerland)

4:00pm - 5:00pm: Poster Session and Break
Session Chair: Dirk Stroobandt
A Linear Divisor Extraction Algorithm
Alan Mishchenko and Robert Brayton (UC Berkeley, USA)
Circuit Obfuscation: Motivations, Assumptions, and Techniques
Mingze Gao, Gang Qu (University of Maryland, USA), Qiang Zhou and Yici Cai (Tsinghua University, China)
Mapping Circuits with Simple Cells from Xor-And-Inverter Graphs
Jody Maick Matos, Marcos H. Backes, Marcus Ritt, Renato P. Ribas and Andre Reis (UFRGS, Brazil)
Towards Optimal Area Synthesis of Small Combinational Circuits
Vinicius Possani, Jody Maick Matos, Marcos Backes, Renato Ribas (UFRGS, Brazil), Leomar Da Rosa Junior (UFPel, Brazil) and Andre Reis (UFRGS, Brazil)
An Efficient Tabu Search Methodology for Port Assignment Problem in High-Level Synthesis
Cong Hao (Waseda University, Japan), Nan Wang (East China University Of Science And Technology, China), Jian-Mo Ni (Shanghai Jiao Tong University, China) and Yoshimura Takeshi (Waseda University, Japan)
C to Verilog Compilation for Software/Hardware Verification
Jiang Long and Robert Brayton (UC Berkeley, USA)

5:00pm: Evening Program
Visit to the Museum and dinner

Saturday June 13, 2015

8:00am - 8:30am: Welcome Breakfast

8:30am - 9:30am: Keynote 3
Session Chair: Gang Qu
An Introduction to Algorithmic Trading
Satrajit Chatterjee, Two Sigma

9:30am - 10:00am: Break

10:00am - 12:00am: Session 4 - Verification and Testing
Session Chair: M. Balakrishnan
Flexibility and Optimization of QBF Skolem-Herbrand Certificates
Valeriy Balabanov, Shuo-Ren Lin and Jie-Hong Roland Jiang (National Taiwan University, Taiwan)
Harnessing Dual-Rail SAT for Logic ECO Synthesis
Tobias Welp (OneSpin Solutions, Inc., Germany) and Smita Krishnaswamy (Columbia University, USA)
Simulation Graphs for Reverse Engineering
Baruch Sterin (UC Berkeley, USA), Mathias Soeken, Rolf Drechsler (University of Bremen, Germany) and Robert Brayton (UC Berkeley, USA)
Delay related testing with two time frame values
Masahiro Fujita (University of Tokyo, Japan)

12:00am - 1:30pm: Lunch

1:30pm - 3:00pm: Session 5 - Logic synthesis for New Gates and HLS
Session Chair: Bob Brayton
MajSynth : An n-input Majority Algebra based Logic Synthesis Tool for Quantum-dot Cellular Automata
Rajeswari Devadoss, Kolin Paul and M Balakrishnan (Indian Institute of Technology Delhi, India)
Threshold Logic Synthesis Based on Cut Pruning
Augusto Neutzling, Jody Maick Matos (UFRGS, Brazil), Alan Mishchenko (UC Berkeley, USA), Renato Ribas and Andre Reis (UFRGS, Brazil)
HOFEX: High Level Optimization of Floating Point Expressions for Implementation on FPGAs
Alireza Mahzoon, Bijan Alizadeh (University of Tehran, Iran) and Masahiro Fujita (University of Tokyo, Japan)

3:00pm - 3:30pm: Break

3:30pm - 4:30pm: Session 6 - Minimization of Logic Functions
Session Chair: Leomar da Rosa
A Method to Minimize Variables for Incompletely Specified Index Generation Functions Using a SAT Solver
Tsutomu Sasao, Ichidou Fumishi and Yukihiro Iguchi ( Meiji University, Japan)
Minimization of Incompletely Specified Functions as Three-Level Logic via Boolean Relations
Anna Bernasconi (Universita' di Pisa, Italy), Robert Brayton (UC Berkeley, USA), Valentina Ciriani, Gabriella Trucco (Universita' di Pisa, Italy) and Tiziano Villa (Universita' di Verona, Italy)

4:30pm - 4:45pm: Closing Remarks
Andre Reis