Program for International Workshop on Logic and Synthesis 2007

Wednesday, May 30

12:00 PM - 1:00 PM

Lunch

 Bay View Deck

1:00 PM - 1:15 PM

Opening Remarks

By General Chair & Program Chairs
  Dockside Room

1:15 PM - 2:35 PM

Latching Values at Right Place and Time

Dockside Room

Chair: Igor Markov (University of Michigan, USA)
Sequential Rewriting and Synthesis
Robert Brayton (University of California, Berkeley, USA); Alan Mishchenko (UC Berkeley, USA)
Minimizing Implementation Costs with End-to-End Retiming
Aaron Hurst (University of California, Berkeley, USA); Alan Mishchenko (UC Berkeley, USA); Robert Brayton (University of California, Berkeley, USA)
FIFO Sizing for High-Performance Pipelines
Cristian Soviani (Columbia University, USA); Stephen Edwards (Columbia University, USA)
Fast Synthesis of Clock Gating from Existing Logic
Aaron Hurst (University of California, Berkeley, USA)

2:45 PM - 3:45 PM

Invited Talk (I): General-Purpose Computing on GPUs, Dr. John Owens (University of California, Davis)

Dockside Room

3:45 PM - 4:45 PM

Poster Session (I) & Coffee Break

Bay View Room
A Comparative Analysis of Gate Leakage and Performance of High-K Nanoscale CMOS Logic Gates
Saraju Mohanty (University of North Texas, USA); Elias Kougianos (Universtiy of North Texas, USA); Rabi Mahapatra (Texas A&M University, USA)
Generation of Multiple Control Toffoli Network Templates
Gerhard Dueck (University of New Brunswick, Canada); Dmitri Maslov (Institute for Quantum Computing/University of Waterloo, Canada)
A Statistic-based Approach to Testability Analysis
Chuang-Chi Chiou (National Tsing Hua University, Taiwan); Chun Yao Wang (University of Tsing Hua, Taiwan)
Leakage Behavior in CMOS and PTL Logic Styles for Logical Synthesis Orientation
Paulo Butzen (UFRGS, Brazil); Rodrigo Mancuso (UFRGS, Brazil); Felipe Schneider (UFRGS, Brazil); Leomar da Rosa Junior (Universidade Federal do Rio Grande do Sul, Brazil); Andre Reis (UFRGS, Brazil); Renato Ribas (UFRGS - Brazil, Brazil)
Static Single Assignment Form and the Dominance Relation
Philip Brisk (Ecole Polytechnique Federale de Lausanne, Switzerland); Majid Sarrafzadeh (UCLA, USA)
A Dual-Vt Assignment Algorithm in SRAM Array Considering Process-Induced Vt Variations
Azadeh Davoodi (University of Wisconsin Madison, USA); Jungseob Lee (University of Wisconsin Madison, USA)
Optimizing Mixed-Radix Ling Adders using Integer Linear Programming
Yi Zhu (University of California, San Diego, USA); Jianhua Liu (University of California, at San Diego, USA); Haikun Zhu (University of California, San Diego, USA); C.k. Cheng (University of California, at San Diego, USA)
ExSDG : Unified Dependence Graph Representation of Hardware Design from System Level down to RTL for Formal Analysis and Verification
Tasuku Nishihara (University of Tokyo, Japan); Daisuke Ando (University of Tokyo, Japan); Takeshi Matsumoto (University of Tokyo, Japan); Masahiro Fujita (University of Tokyo, Japan)
Combinational and Sequential Mapping with Priority Cuts
Alan Mishchenko (UC Berkeley, USA); Sungmin Cho (UC Berkeley, USA); Satrajit Chatterjee (UC Berkeley, USA); Robert Brayton (University of California, Berkeley, USA)
Efficient MRF-based Noise-immune Sub-threshold Logic Circuit Design
Charu Nagpal (Texas A&M University, USA); Rajesh Garg (Texas A&M University, USA); Sunil Khatri (Texas A&M University, USA)

4:45 PM - 6:05 PM

Design Test, Debug, and Correction

Dockside Room

Chair: Sunil Khatri (Texas A&M University, USA)
Automatic Error Diagnosis and Correction for RTL Designs
Kai-hui Chang (University of Michigan, USA); Ilya Wagner (University of Michigan, USA); Valeria Bertacco (University of Michigan, USA); Igor Markov (University of Michigan, USA)
Automating Post-Silicon Debugging and Repair
Kai-hui Chang (University of Michigan, USA); Igor Markov (University of Michigan, USA); Valeria Bertacco (University of Michigan, USA)
Stimulus Generation for Constrained Random Simulation
Nathan Kitchen (University of California - Berkeley, USA); Andreas Kuehlmann (Cadence, USA)
An Enhanced Sequential Test Generation Framework Based on Boolean Satisfiability
Feijun Zheng (Zhejiang University, P.R. China); Kwang-Ting Cheng (University of California, Santa Barbara, USA); Xiaolang Yan (Zhejiang University, P.R. China)

7:00 PM - 9:00 PM

Dinner

Paradise Point Resort
Garden Room (or lawn venue)

Thursday, May 31

7:30 AM - 8:30 AM

Breakfast

Bay View Deck

8:30 AM - 9:50 AM

Circuit Tradeoffs in Combinational Synthesis

Dockside Room

Chair: Alan Mishchenko (UC Berkeley, USA)
Technology Mapping Using a Fixed Delay and Variable Area-Power Model
Xinning Wang (Strategic CAD Labs, Intel, USA); Steven Burns (Strtegic CAD Labs, Intel Corporation, USA)
Design of a Parallel-Prefix Adder Architecture with Efficient Timing-Area Tradeoff Characteristic
Sabyasachi Das (Synplicity Inc, USA); Sunil Khatri (Texas A&M University, USA)
Timing-constrained Area Minimization Algorithm for Parallel Prefix Adders
Taeko Matsunaga (Waseda University, Japan); Yusuke Matsunaga (Kyushu University, Japan)
Timing-Driven Synthesis for Fast Barrel Shifters
Sabyasachi Das (Synplicity Inc, USA); Sunil Khatri (Texas A&M University, USA)

10:00 AM - 11:00 AM

Invited Talk (II): Gene Regulatory Networks, Dr. Aniruddha Datta (Texas A&M University)

Dockside Room

11:00 AM - 11:15 AM

Coffeee Break

Bay View Deck

11:15 AM - 12:30 PM

Programming Challenge

Dockside Room

12:30 PM - 1:30 PM

Lunch

Bay View Deck

1:30 PM - 2:50 PM

Synthesis for Reliable and Not So Reliable Circuits

Dockside Room

Chair: Timothy Kam (Intel, USA)
The Synthesis of Stochastic Logic for Nanoscale Computation
Weikang Qian (University of Minnesota, USA); John Backes (University of Minnesota, USA); Marc Riedel (Unviersity of Minnesota, USA)
Probabilistic Decision Diagrams for Exact Probabilistic Analysis
Afshin Abdollahi (University of California, Riverside, USA)
Enhancing Design Robustness With Reliability-Aware Resynthesis and Logic Simulation
Smita Krishnaswamy (University of Michigan, USA); Stephen Plaza (University of Michigan, USA); Igor Markov (University of Michigan, USA); John Hayes (University of Michigan, USA)
Optimization for Timing-Robust Asynchronous Circuits Based on Eager Evaluation
Cheoljoo Jeong (Columbia University, USA); Steve Nowick (Columbia University, USA)

2:50 PM - 3:40 PM

Poster Session (II) & Coffee Break

Bay View Room
Interdependency Study of Process and Design Parameter Scaling for Power Optimization of Nano-CMOS Circuits Under Process Variation
Saraju Mohanty (University of North Texas, USA); Elias Kougianos (Universtiy of North Texas, USA); Dhruva Ghai (Universtiy of North Texas, USA); Priyadarsan Patra (Intel Corporation, USA)
Escaping Local Minima in Logic Synthesis
Eugene Goldberg (Cadence Design Systems, USA)
A Non-ILP Based Threshold Logic Synthesis Methodology
Tejaswi Gowda (Arizona State University, USA); Sarma Vrudhula (Arizona State University, USA); Goran Konjevod (Arizona State University, USA)
Benchmarking Method and Designs Targeting Logic Synthesis for FPGAs
Joachim Pistorius (Altera Corporation, USA); Mike Hutton (Altera, USA); Alan Mishchenko (UC Berkeley, USA); Robert Brayton (University of California, Berkeley, USA)
Design, Synthesis and Evaluation of Heterogeneous FPGA With Mixed LUTs and Macro-Gates
Yu Hu (University of California Los Angeles, USA); Satyaki Das (Xilinx Inc., USA); Lei He (University of California, Los Angeles, USA)
Multiplexer Optimization for High-Level Synthesis of Static Single Assignment Form Programs
Philip Brisk (Ecole Polytechnique Federale de Lausanne, Switzerland); Majid Sarrafzadeh (UCLA, USA)
A Hardware Approach for Approximate, Efficient Logarithm and Antilogarithm Computations
Suganth Paul (Texas A&M University, USA); Nikhil Jayakumar (University of Colorado at Boulder, USA); Sunil Khatri (Texas A&M University, USA)
A Robust Window-based Multi-node Minimization Technique using Boolean Relations
Jeff Cobb (Dept of Electrical and Computer Engg, USA); Kanupriya Gulati (Texas A&M University, USA); Sunil Khatri (Texas A&M University, USA)
A Simple Approach to Partition a Set of Logic Input Variables
Reginaldo Tavares (Universidade Federal de Pelotas, Brazil); Ricardo Reis (Universidade Federal do Rio Grande do Sul, Brazil)

3:40 PM - 5:00 PM

Verification Advances

Dockside Room

Chair: Christian Stangier (Mentor Graphics, USA)
Symmetry Detection for Large Multi-output Functions
Donald Chai (University of California at Berkeley, USA); Andreas Kuehlmann (Cadence, USA)
Automated Extraction of Inductive Invariants to Aid Model Checking
Michael Case (University of California, Berkeley, USA); Alan Mishchenko (UC Berkeley, USA); Robert Brayton (University of California, Berkeley, USA)
A Hybrid Approach for Equivalence Checking Between System Level and RTL Descriptions
Bijan Alizadeh (University of Tokyo, Japan); Masahiro Fujita (University opf Tokyo, Japan)
MCjammer: An Adaptive Verification Tool for Multi-core and Multi-processor Designs
Ilya Wagner (University of Michigan, USA); Valeria Bertacco (University of Michigan, USA)

7:00 PM - 10:00 PM

Dinner Cruise

Friday, Jun 1

8:00 AM - 9:00 AM

Breakfast

Bay View Deck

9:00 AM - 10:20 AM

Provably Optimal and Practically Scalable Techniques for Synthesis

Dockside Room

Valeria Bertacco (University of Michigan, USA)
Optimal Polynomial-Time Interprocedural Register Allocation for High-Level Synthesis Using SSA Form
Philip Brisk (Ecole Polytechnique Federale de Lausanne, Switzerland); Paolo Ienne (EPFL, Switzerland); Ajay Verma (Ecole Polytechnique Federale de Lausanne (EPFL), Switzerland)
Exploiting Symmetry in SAT Based Boolean Matching for Heterogeneous FPGA Technology Mapping
Yu Hu (University of California Los Angeles, USA); Victor Shih (University of California Los Angeles, USA); Rupak Majumdar (UCLA, USA); Lei He (University of California, Los Angeles, USA)
Fast Minimum-Register Retiming via Binary Maximum-Flow
Aaron Hurst (University of California, Berkeley, USA); Alan Mishchenko (UC Berkeley, USA); Robert Brayton (University of California, Berkeley, USA)
A Linear Time Algorithm for Optimum Tree Placement
Satrajit Chatterjee (University of California at Berkeley, USA); Zile Wei (U. C. Berkeley, USA); Alan Mishchenko (UC Berkeley, USA); Robert Brayton (University of California, Berkeley, USA)

10:20 AM - 10:40 AM

Coffee Break

Bay View Deck

10:40 AM - 12:00 PM

Applications of Boolean Satisfiability

Dockside Room

Chair: Christoph Albrecht (Cadence Berkeley Laboratories, USA)
Incremental Learning Approach and SAT Model for Boolean Matching with Don't Cares
Kuo-Hua Wang (Fu Jen Cathoilic University, Taiwan); Chung-Ming Chan (Fu Jen Catholic University, Taiwan)
Toggle: A Coverage-guided Random Stimulus Generator
Stephen Plaza (University of Michigan, USA); Igor Markov (University of Michigan, USA); Valeria Bertacco (University of Michigan, USA)
SAT-Based Logic Optimization and Resynthesis
Alan Mishchenko (UC Berkeley, USA); Robert Brayton (University of California, Berkeley, USA); Jie-Hong Jiang (National Taiwan University, Taiwan); Stephen Jang (Xilinx, Inc, USA)
Scalable Exploration of Functional Dependency by Interpolation and Incremental SAT Solving
Chih-Chun Lee (National Taiwan University, Taiwan); Jie-Hong Jiang (National Taiwan University, Taiwan); Chung-Yang Huang (National Taiwan University, Taiwan); Alan Mishchenko (UC Berkeley, USA)

12:00 PM - 1:00 PM

Lunch

Bay View Deck

1:00 PM - 2:20 PM

Technology-Independent Synthesis of Combinational Logic

Dockside Room

Chair: Marc Riedel (Unviersity of Minnesota, USA)
Sum-of-Generalized Products Expressions: Applications and Minimization
Tsutomu Sasao (Kyushu Inst. of Technology, Japan)
Toggle Equivalence Preserving (TEP) Logic Optimization
Eugene Goldberg (Cadence Design Systems, USA); Kanupriya Gulati (Texas A&M University, USA); Sunil Khatri (Texas A&M University, USA)
FIREwork: Redundancy Identification and Removal for Large Combinational Circuits
Maxim Teslenko (Royal Institute of Technology, KTH, Stockholm, Sweden); Elena Dubrova (Royal Institute of Technology, Sweden); Hannu Tenhunen (Royal Institute of Technology, Sweden)
A New Methodology for Quantum Circuit Synthesis: CNOT-Based Circuits as an Example
Mehdi Saeedi (Amirkabir University of Technology, Iran); Mehdi Sedighi (Amirkabir University of Technology, Iran); Morteza Saheb Zamani (Amirkabir University of Technology, Iran)

2:20 PM - 2:35 PM

Closing Remarks

By General Chair & Program Chair
Dockside Room

2:35 PM - 3:30 PM

TPC Planning Meeting for IWLS2008