IWLS 2006 Program

Wednesday, June 7

12:00 - 1:00 : Lunch

1:00 - 3:00 : Synthesis
chair: Christian Stangier
Factor Cuts
   Satrajit Chatterjee, Alan Mishchenko, and Robert Brayton
Integrated Logic Synthesis Using Simulated Annealing
   Petra Farm, Elena Dubrova, and Andreas Kuehlmann
Scalable Logic Synthesis using a Simple Circuit Structure
   Alan Mishchenko and Robert Brayton
Generalized Buffering of PTL Logic Stages using Boolean Division and Don't Cares
   Rajesh Garg and Sunil Khatri

3:00 - 3:15 : Two-Minute Poster Presentations

3:15 - 4:00 : Poster Session 1
Efficient Techniques for Large BDDs
   Kazuya Shinozuka
Boolean Function Minimization, Information Theoretic Approach
   Javad Safaei Mehranpour and Hamid Beigy
Stochastic Programming Based Optimization Framework in Presence of Variability
   Vishal Khandelwal and Ankur Srivastava
Performance Analysis of the Asynchronous Nonlinear Pipeline using the Max-Plus Algebra
   Jian Ruan, Lei Wang, Zhiying Wang, and Kui Dai
An Approximate Method by Queuing Network Modeling for Performance Evaluation of Asynchronous Pipeline
   Lei Wang, Zhiying Wang, and Kui Dai
A Low Power Overhead Bus Coding Technique for Minimizing Inductive Crosstalk in VLSI Connectors
   K. S. Sainarayanan, J. V. R. Ravindra, and M. B. Srinivas

4:00 - 5:30 : Physical Issues
chair: Christoph Albrecht
Design and Analysis of ``Tree + Local Meshes'' Clock Architecture
   Rajeev Murgai and Gustavo Wilke
An Improved Sliding Window Scheme for Clock Mesh Analysis
   Rajeev Murgai and Subodh Reddy
Keeping Physical Synthesis Safe and Sound
   Kai-hui Chang, Igor Markov, and Valeria Bertacco

5:30 - 7:00 : IWLS Programming Challenge
chair: Christoph Albrecht, Florian Krohm, Bob Brayton, and Valavan Manohararajah

7:00 - 9:00 : Dinner

Thursday, June 8

7:30 - 8:30 : Breakfast

8:30 - 10:00 : High-Level Synthesis
chair: Marc Riedel
A Design Method of Address Generators Using Hash Memories
   Tsutomu Sasao
Optimizing Fixed-Size Bit-Vector Arithmetic using Finite Ring Algebra
   Sivaram Gopalakrishnan, Priyank Kalla, and Florian Enescu
Protocol Wrapper Generation from Statement Based Specification
   Yuji Ishikawa, Shota Watanabe, Kenshu Seto, and Masahiro Fujita

10:00 - 10:15 : Two-Minute Poster Presentations

10:15 - 11:00 : Poster Session 2
A Fully Multiplexer-based Implementation of Redundant Number System
   Sreehari Veeramachaneni, Pradeep Yarlagadda, and M. B. Srinivas
Fast CMOS Logic Style Using Minimum Transistor Stack for Pull-up and Pull-down Networks
   Felipe Schneider, Renato Ribas, and Andre Reis
BDDs and transistor networks with minimum pull-up/pull-down chains
   Leomar da Rosa Junior, Felipe Marques, Tiago Cardoso, Renato Ribas, and Andre Reis
On prefix graph generation algorithm for binary addition under area-delay trade-off
   Taeko Matsunaga and Yusuke Matsunaga
Analysis of Maximum Switching Activities in Sequential Circuits for Power Supply Integrity Validation
   Hiroyuki Higuchi
Automatic Protocol Transducer Synthesis aiming at facilitating IP-Reuse
   Shota Watanabe, Kenshu Seto, Yuji Ishikawa, Satoshi Komatsu, and Masahiro Fujita

11:00 - 1:00 : Invited Session: New Directions for Logic Synthesis
chair: Marc Riedel
Engineering New Molecules for Programming Complex Cellular Systems
   Christina Smolke, Caltech
Analysis of Functions, Networks, and Phenotypes by Integrative Genomics
   Jasmine Zhou, USC
Synthetically Modified Structural Proteins: Self-Assembling Building Blocks for Nanoscale Materials
   Matt Francis, U. C. Berkeley

1:00 - 2:30 : Lunch and Planning for IWLS 2007

2:30 - 6:30 : Social Event

6:30 - 8:00 : Dinner

Friday, June 9

7:30 - 8:30 : Breakfast

8:30 - 10:00 : Verification 1
chair: Mukul Prasad
Inductively Finding a Reachable State Space Over-Approximation
   Michael Case, Alan Mishchenko, and Robert Brayton
Improvements to Combinational Equivalence Checking
   Alan Mishchenko, Satrajit Chatterjee, Robert Brayton, and Niklas Een
Advances and Insights into Parallel SAT Solving
   Ian Kountanis, Stephen Plaza, Zaher Andraus, Valeria Bertacco, and Trevor Mudge

10:00 - 10:15 : Two-Minute Poster Presentations

10:15 - 11:00 : Poster Session 3
Design of a Reversible PLD Architecture
   Jae-Jin Lee and Gi-Yong Song
Reversible Logic Implementation of BCD Subtractor for IEEE 754r Format
   Himanshu Thapliyal
Synthesis of a Reversible Bit-Serial GF(2m) Systolic multiplier using a Novel Reversible Gate
   Kamala Ramachandruni and Srinivas Mandalika
Design of Asynchronous Circuits on Top of Synchronous FPGAs
   Renato Mocho, Giovani sartori, Renato Ribas, and Andre Reis
On Automatic Synthesis of Data Dependent Micropipelines
   Alexander Smirnov, Alexander Taubin, and Mark Karpovsky
A Compositional Approach to Symmetry Detection in Circuits
   Donald Chai and Andreas Kuehlmann

11:00 - 12:30 : Variability
chair: Andreas Kuehlmann
Variability Driven Gate Sizing for Binning Yield Optimization
   Azadeh Davoodi and Ankur Srivastava
Latch-Based Design under Process Variation
   Aaron Hurst and Robert Brayton
Efficient and Accurate Statistical Timing Analysis for Non-Linear, Non-Gaussian Variability With Incremental Attributes
   Ashish Dobhal, Vishal Khandelwal, and Ankur Srivastava

12:30 - 1:30 : Lunch

1:30 - 3:00 : Verification 2
chair: Michael Theobald
Design Error Detection in System-Level Designs by Dependence Analysis and Formal Checker
   Daisuke Ando, Tasuku Nishihara, Takeshi Matsumoto, Masahiro Fujita, and Shunsuke Sasaki
Verification after Synthesis
   Alan Mishchenko and Robert Brayton
Improved Threshold Voltage Assignment via Combinatorial Implementation Selection
   Soheil Ghiasi