IWLS-98 Program and WebLinks

Sunday, June 7

6:00-10:00pm: Dinner reception and Poster Hanging

(NB: All posters will remain up for the duration of the meeting. Poster presenters guarantee to be present at their poster at the scheduled time, but may be present at other times)

Monday, June 8

8:30-9:50 Session 1: Asynchronous Synthesis and Verification

  1. A Symbolic Representation of Asynchronous Networks of Synchronous Processes
    Amar Bouali, Robert De Simone
  2. Hiding Memory Elements in Induced Hierarchical Verification of Speed-Independent Circuits Author Link
    Peter A Beerel, Vida Vakilotojar
  3. Parity-OBDDs - a BDD Structure for Probabilistic Verification
    Harald Sack, Christoph Meinel
  4. Satisfiability-Based Algorithms for 0-1 Integer ProgrammingAuthor Link
  5. Vasco M Manquinho, Joao P Marques Silva, Arlindo L Oliveira, Karem A. Sakallah

9:50-10:30 Poster Session 1: Verification, Asynchronous and Sequential Synthesis and BREAK

  1. VHDL Based Formal Verification Of Risc Piplined Processor Infinity : A Case Study
    Fahim Rahim-Sarwary, Rajesh K Bawa, Amara Amara
  2. On the Efficiency of Learning Techniques for Combinational Equivalence Checking
    Koen Van Eijk, Geert Janssen
  3. Automatic Partitioning for Efficient Combinational Verification
    Rajarshi Mukherjee, Jawahar Jain, Koichiro Takayama, Masahiro Fujita
  4. Sequential Logic Optimization with Symbolic and ATPG-Based Techniques
    Luis A Entrena, Jose A Espejo, Enrique San Millan, Silvia Chiusano, Fulvio Corno
  5. Storage Correspondence for Large Sequential Circuits
    Vamsi Boppana, Rajarshi Mukherji, Masahiro Fujita
  6. MINIMALIST: An Environment for the Synthesis and Verification of Burst-Mode Asynchronous Machines
    Robert M Fuhrer, Steven M Nowick, Michael Theobald, Niraj K Jha, Luis Plana
  7. Towards Multi-level Synthesis for Asynchronous Logic
    Jeroen Rutten, Michel Berkelaar
  8. Optimal design of synchronous circuits using software pipelining techniques
    Francois R Boyer, Mostapha Aboulhamid, Yvon Savaria, Imed E Bennour
  9. Control Synthesis for Long Datapath Architectures
    Darren C Cronquist, Carl Ebeling
  10. Sequential Synthesis: A Game-theoretic Perspective
    Sriram C Krishnan, Robert K Brayton
  11. CRC Benchmarks
    Alan J Coppola

10:30-11:50 Session 2: Retiming and Sequential Synthesis

  1. How Powerful is Retiming?
    Hai Zhou, Vigyan Singhal, Adnan Aziz
  2. An Integrated Retiming and Resynthesis Approach to Performance Optimization
    Peichen Pan, Ananth Gopalakrishnan
  3. Combining logic synthesis and retiming
    Harm Arts
  4. Exact Optimal State Minimization for 2-Level Output Logic
    Robert M Fuhrer, Steven M Nowick

11:50-1:00 Focus Groups I

1:00-2:00 LUNCH

2:00-3:20 Session 3: Dynamic and PTL synthesis

  1. Dynamic Logic Synthesis using Alternating Dynamic and Static GatesAuthor Link
    Tyler Thorp, Gin Yee, Carl Sechen
  2. Buffer Minimization in Pass Transistor LogicAuthor Link
    Hai Zhou, Adnan Aziz
  3. Simultaneous PTL Buffer Insertion and Sizing for Minimizing Elmore DelayAuthor Link
    I-Min Liu, Tai-Hung Liu, Hai Zhou, Adnan Aziz
  4. Area-Oriented Synthesis for Pass-Transistor Logic
    Rajat Chaudhry, Tai-Hung Liu, Jeffrey L Burns, Adnan Aziz

3:20-4:00 Poster Session 2: Optimization and Technology Mapping and BREAK

  1. Exact Circuit Synthesis
    Rolf Drechsler, Wolfgang Guenther
  2. Solving Dichotomy-based Constrahined Encoding With Twin Graph Coloring
    Olivier S Coudert
  3. Cover Homology
    Alan J Coppola
  4. Improved Logic Synthesis Using Boolean Transforms
    James Jacob, Vishwani D Agrawal
  5. Managing Dual Logical and Physical Hierarchies for Post-Layout Resynthesis and Optimization
    David E Wallace
  6. Systematic Logic Design
    Sandor Vincze
  7. Performance Optimization for MUX-Based FPGAs after Technology Mapping
    Luis A Entrena, Jose A Espejo, Enrique San Millan, Emilio Olias
  8. Efficient Logic Synthesis for FPGAs and PLDs with Information Relationship Measures
    Lech Jozwiak
  9. Performance Driven Synthesis for Pass-Transistor Logic Circuits
    Tai-Hung Liu, Jeffrey L Burns, Adnan Aziz
  10. On Accelerating Pattern Matching for Technology Mapping
    Yusuke Matsunaga

4:00-5:20 Session 4: Verification of Sequential Networks

  1. Efficient Coverage Directed State Space Search
    Malay K Ganai, Adnan Aziz
  2. Structural Methods Applied to the Symbolic Analysis of Petri Nets
    Enric Pastor, Jordi Cortadella
  3. Symbolic Reachability Analysis of Large Finite State Machines Using Don't CaresAuthor Link
    Youpyo Hong, Peter A Beerel
  4. Using combinational verification for sequential circuitsAuthor Link
    Rajeev K Ranjan

6:00-8:00 Dinner

8:00-10:00 BOF sessions

  1. Design of Experiments in Logic Synthesis. Coordinator: Franc Brglez

Tuesday, June 9

8:30-9:50 Session 5: BDDs

  1. BDD Package Benchmarking using Entropy-Signature Invariant Mutant Circuit ClassesAuthor Link
    Justin E Harlow, Franc Brglez
  2. Sample Method for Minimization of OBDDs
    Anna Slobodova, Christoph Meinel
  3. Preventing OBDD blow-ups via domain transformations guided by high-level specifications
    Eugene I Goldberg, Yuji Kukimoto, Robert K Brayton
  4. Optimizing Pseudo-Symmetric Binary Decision Diagrams using Multiple Symmetries
    Wei Wang, Malgorzata Chrzanowska-Jeske

9:50-10:30 Poster Session 3: BDDS and Low Power Synthesis and BREAK

  1. Fast Exact Minimization of BDDs
    Rolf Drechsler, Nicole Drechsler, Wolfgang Guenther
  2. Synthesis of Fully Testable High Speed Circuits Derived from Decision Diagrams Author Link
    Harry Hengster, Bernd Becker
  3. Binary Decision Diagrams and the Multiple Variable Order Problem Author Link
    Christian Stangier, Gianpiero Cabodi, Stefano Quer, Christoph Meinel, Harald Sack, Anna Slobodova
  4. Don't Care FDD Minimization by Interpolation
    Zeljko Zilic
  5. Long and Short Path Sizing for Delay - Power Performance ManagementAuthor Link
    Nadine Azemard-Crestani, Daniel P Auvergne, Severine Cremoux
  6. A Novel Spatial Technique for the Complexity Estimation in Synthesis
    Elie Torbey, John Knight
  7. Low Power PLAs
    Reginaldo N Tavares, Michel R Berkelaar, Jochen A Jess

11:50-1:00 Focus Groups II

1:00-2:00 LUNCH

2:00-3:20 Session 7: Analysis: Power, Timing and Testability

  1. A Linear Programming Approach for the Estimation of an Upper Bound on the Maximum Power of CMOS Circuits
    Etienne Jacobs, Michel Berkelaar
  2. Efficient computation of Timed Transition Relations
    Stefano Quer, Gianpiero Cabodi, Paolo E Camurati, Luciano Lavagno
  3. Delay Characterization of Combinational ModulesAuthor Link
    Yuji Kukimoto, Robert K Brayton
  4. An Exact Solution to the Minimum-Size Test Pattern ProblemAuthor Link
    Paulo F Flores, Horacio C Neto, Joao P Marques Silva

3:20-3:45 BREAK

3:45-5:15 Panel: Gigahertz Design Challenges to Logic Synthesis and Beyond.

5:30 Board bus for Squaw Valley

6:00-8:00 Banquet: Squaw Valley

10:00 First Return Bus To Granlibakken

Wednesday, June 10

8:30-9:50 Session 8: Decomposition and Optimization

  1. DECOMPOS: An Integrated System for Functional Decomposition
    Tsutomu Sasao
  2. Finding complex disjunctive decompositions of logic functions
    Maurizio Damiani, Valeria Bertacco
  3. Multi-level Logic Optimization Based on Wave Synthesis of Permissible Mutation Functions (WASP)Author Link
    Andrej Zemva, Franc Brglez, Baldomir Zajc
  4. Implementation and Use of SPFDs
    Robert K Brayton, Subarna Sinha

9:50-10:15 BREAK

10:15-11:35 Session 9: Synthesis, Physical Design an(d) Evolution

  1. Incremental Timing Optimization for Physical Design by Interacting Logic Restructuring and Layout
    Mike Lee
  2. Layout-oriented Synthesis of PTL Circuits based on BDDs
    F Ferrandi
  3. Wireplanning in Logic Synthesis
    Wilsin Gosti, Amit Narayan, Robert K Brayton, Alberto L Sangiovanni-Vincentelli
  4. Efficient Graph Coloring by Evolutionary Algorithms
    Nicole Drechsler, Wolfgang Guenther, Rolf Drechsler

11:35-12:30 Focus Groups III: Wrapup