+session: Technology Mapping I
+moderator: S. Malik (A. Saldanha)


+number: 34
+title:	Efficient Orthonormality Testing for Synthesis with Pass-Transistor Selectors
+authors: M. Berkelaar and L. P. P. P. van Ginneken

+number: 42
+title:	Buffer Tree Construction and Gate Transformation for the Fanout Problem
+authors: R. J. Carragher and M. Fujita and C.-K. Cheng

+number: 24
+title:	Phase Optimization in Technology Mapping
+authors: Y. Matsunaga


+number: 6
+title:	Delay Abstraction in Combinational Logic Circuits
+authors: N. Kobayashi and S. Malik

+number: 33
+title:	Delay Optimization of Combinational Circuits by Logic Clause Analysis
+authors: B. Rohfleisch and B. Wurth and K. Antreich

+number: 28
+title:	A New Method for Performance Oriented Logic Extraction
+authors: H. Vaishnav and M. Pedram

+number: 9
+title:	Delay Minimal Decomposition of Multiplexers in Technology Mapping
+authors: S. Thakur and D. F. Wong and S. Krishnamoorthy and P.  Moceyunas

+session: FSM Synthesis I
+moderator: R. Brayton (E. Sentovich)


+number: 37
+title:	Implicit State Minimization of Non-Deterministic FSM's
+authors: T. Kam and T. Villa and R. K. Brayton and A. Sangiovanni-Vincentelli

+number: 25
+title:	Implicit Generation of Prime Compatibles for Incompletely Specified Finite State Machines
+authors: H. Higuchi and Y. Matsunaga

+number: 32
+title:	The Influence of Two Level Optimization on the Area and Routability of FSMs Embedded in Lookup Table FPGAs
+authors: D. Bostick and M. Lightner


+number: 23
+title:	The Validity of Retiming Sequential Circuits
+authors: V. Singhal and C. Pixley and R. Rudell and R. K. Brayton

+number: 47
+title:	Stochastic Analysis of Large Digital Systems
+authors: A. Srinivasan and K. S. Trivedi

+session: FSM Traversal
+moderator: J. C. Madre (R. Rudell)


+number: 49
+title:	Approximate Finite State Machine Traversal: Extensions and New Results
+authors: H. Cho and G. D. Hachtel and E. Macii and M. Poncino and K. Ravi and F. Somenzi

+number: 36
+title:	Incremental Methods for FSM Traversal
+authors: G. M. Swamy and V. Singhal and R. K. Brayton

+number: 21
+title:	Incremental FSM Re-Encoding for Simplifying Verification by Symbolic Traversal
+authors: S. Quer and G. Cabodi and P. Camurati and L. Lavagno and E. M.  Sentovich and R. K. Brayton


+number: 44
+title:	Efficient BDD Algorithms for FSM Synthesis and Verification
+authors: R. K. Ranjan and A. Aziz and R. K. Brayton and B. Plessier and C. Pixley

+number: 18
+title:	Detection of Equivalent State Variables in Finite State Machine Verification
+authors: C. A. J. van Eijk and J. A. G. Jess

+session: Low Power
+moderator: M. Pedram (S. Devadas)


+number: 13
+title:	Optimal Synthesis of Gated Clocks for Low Power Finite State Machines
+authors: L. Benini and G. De Micheli

+number: 45
+title:	Data Sequencing for Minimum-Transition Transmission
+authors: R. Murgai and M. Fujita and S. C. Krishnan

+number: 29
+title:	Performance-Directed Synthesis of Finite-State Systems
+authors: M. Damiani


+number: 22
+title:	Guarded Evaluation: Pushing Power Management to Logic Synthesis/Design
+authors: V. Tiwari and S. Malik and P. Ashar

+number: 16
+title:	Transition Probability Estimation for Combinational and Sequential Circuits
+authors: P. H .Schneider and B. Wurth

+session: BDDs
+moderator: C. Meinel (S. Minato)


+number: 35
+title:	Simulated Annealing to Improve Variable Orderings for OBDDs
+authors: B. Bollig and M. Loebbing and I. Wegener

+number: 48
+title:	Who Are the Variables in Your Neighborhood
+authors: S. Panda and F. Somenzi

+number: 38
+title:	BDD Minimization by Truth Table Permutations
+authors: M. Fujita and Y. Kukimoto and R. K. Brayton


+number: 11
+title:	BDD-Based Manipulation of Polynomials and its Applications
+authors: S. Minato

+number: 5
+title:	Dynamic Global Rebuilding
+authors: C. Meinel and A. Slobodova

+number: 1
+title:	A Genetic Algorithm for Variable Ordering of OBDDs
+authors: R. Drechsler and B. Becker and N. Goeckel

+session: Combinational Synthesis
+moderator: G. Hachtel (A. Wang)


+number: 40
+title:	Fast Discrete Function evaluation using Decision Diagrams
+authors: P. C. McGeer and K. L. McMillan and A. Saldanha and A. L. Sangiovanni-Vincentelli and P. Scaglia

+number: 46
+title:	Logic Synthesis for a Single Large Look-up Table
+authors: R. Murgai and F. Hirose and M. Fujita


+number: 39
+title:	New Ideas for Solving Covering Problems
+authors: O. Coudert

+number: 50
+title:	Observations on Verification Techniques Based on Learning
+authors:  R. Mukherjee and J. Jain and M. Fujita and J. A. Abraham and D. S. Fussell

+number: 10
+title:	Multilevel Logic Design for Testability using Orthonormal Expansions
+authors: R. Takahashi and T. Nanya

+number: 20
+title:	Efficient Generator of Adders
+authors: M. Belrhiti and G. Bosco and A. Guyot

+session: FSM Synthesis II
+moderator: N. Shenoy (Y. Matsunaga)


+number: 30
+title:	Synthesizing Interacting Finite State Machines
+authors: A. Aziz and F. Balarin and R. K. Brayton

+number: 31
+title:	Symbolic Hazard-Free Minimization and Encoding of Asynchronous Finite State Machines
+authors: R. M. Fuhrer and B. Lin and S. M. Nowick

+number: 17
+title:	Exploiting Power-up Delay for Sequential Optimization
+authors: V. Singhal and C. Pixley and A. Aziz and R. K. Brayton


+number: 26
+title:	Formal Design of a Class of Computers. Its low stage: linear microprogramming
+authors: L.-G. Wang

+number: 27
+title:	Formal Design of a Class of Computers. Its high stage: abstract microprogramming
+authors: L.-G. Wang

+session: EXOR-Based Synthesis
+moderator: A. Sarabi (J. Jess)


+number: 43
+title:	Synthesis of AND-EXOR expressions via Satisfiability
+authors: M. Escobar and F. Somenzi

+number: 3
+title:	A Design Method for AND-OR-EXOR Three-Level Networks
+authors:  T. Sasao

+number: 2
+title:	OKFDDs versus OBDDs and OFDDs
+authors: B. Becker and R. Drechsler and M. Theobald


+number: 8
+title:	Universal XOR Canonical Forms of Boolean Functions and its Subset Family of AND/OR/XOR Canonical Forms
+authors: M. A. Perkowski and A. Sarabi and F. R. Beyl

+number: 4
+title:	Parity Function Detection and Realization Using a Small Set of Spectral Coefficients
+authors:  M. A. Thornton and V. S. S. Nair

+session: Technology Mapping II
+moderator: B. Wurth (E. Macii)


+number: 51
+title: An Exact Algorithm for FPGA Rectification
+authors: H. Shin and F. Somenzi

+number: 12
+title:	Limits of Using Signatures for Permutation Independent Boolean Comparison
+authors: J. Mohnke and P. Molitor and S. Malik

+number: 14
+title:	Generalized Matching: A New Approach to Concurrent Logic Optimization and Library Binding
+authors: L. Benini and M. Favalli and G. De Micheli


+number: 15
+title:	Functional Multiple-Output Decomposition for Lookup-Table Based FPGAs
+authors: B. Wurth and K. Eckl

+number: 41
+title:	Logic Rectification and Synthesis for Engineering Change
+authors: C.-C. Lin and K.-C. Chen and D. I. Cheng and M. Marek-Sadowska

+number: 7
+title:	Hierarchical Technology Mapping
+authors: V. Kommu and C. Do

+number: 19
+title:	FPGA Synthesis for Cellular Processing
+authors: S. Waldschmidt and C. Hochberger