International Workshop on Logic Synthesis
         Research Triangle Park, North Carolina, USA
                May 23-26, 1989

   Sponsored by the Microelectronics Center of North Carolina (MCNC)
           In Cooperation with acme SIDGA


 1.1  Two Fast Two-Level Minimizers for Multi-Level Logic Synthesis,
    H. Savoj, A. Malik, R. Brayton, University Of California-Berkeley
 1.2  An Efficient Output Phase Assignment for MultileveI Logic Minimization, 
     C-L Wey, S-M Chang, Michigan State University; J-Y Jou, AT&T Bell Laboratories
 1.3  Experiments with Global-Flow Analysis,
     S. Parkes, R. Saleh, University of Illinois; R. Rudell. Synopsys, Inc.
2.1  Introduction to poster presentations
        Presenters'. R. Amann, University of Karlsruhe:. a. Kapoor,    '
             Texas Instruments: J. Theeuwen. Eindhoven University of Technology;
             H. Sato, Fujitsu: R. Leveugle, INPG/CSI: K. McElvain, Silicon
            Compiler Systems; K. De, Texas Instruments; G. Saucier,
             lNPG/CS1: C. Kingsley, VLST Technology; VV. Wolf. AT&.T Bell
            Labs'. S. Malik, UC-Berkeley: M. Kotliar, UNC-Chapel Hill.,
            L. Lavagno, UC-Berkeley: E. Sentovich. UC-Berkeley
3.1 On the Relationship Between Area Optimization and Multifault Testability of multilevel Logic, 
  G. Hachtel, R. Jacoby, University of Colorado; K. Keutzer. AT&T Bell Laboratories; C. Morison, University of Colorado
3.2 Consistency and Observability invariance in Multi-Level Logic Synthesis, 
    P. McGeer, R. Brayton, University of California -Berkeley
3.3 On Computing and Approximating the Observability Don't Care Set, 
    G. Hachtel. R. Jacoby, P. Moceyunas, University of Colorado
3.4 Boolean Relations, R. Brayton,
    University of California-Berkeley: F. Somenzi, SGS-Thomson
4.1 BESTMAP: Behavioral Synthesis From C.,
    J-Y Jou R. Ernst, S. Sudawala, A. Prahbu, 
4.2 A Unified Logic Synthesis System: ZEPHCAD, 
    H. Sato, Fujitsu, Ltd.: Y. Matsunaga, M. Fujita, Fujitsu Laboratories Ltd,: Y. Sugiura, Fujitsu, Ltd.
5.1 Retiming and Resynthesis with Combinational Techniques,
    S. Malik, E. Sentovich. R. Brayton, A. Sangiovanni-Vincentelli, University of California-Berkeley
5.2 Synchronous Logic Synthesis. G. De Micheli. Stanford University
5.3 Restructuring State Machines and State Assignment: Relationship to Minimizing Logic Across Latch Boundaries.
    B. Lin. A. Newton, University of California-Berkeley
6.1 Race-Free Time-Optimised Synthesis of Asynchronous Interface Circuits, 
    P. Van Meerbergen, F. Catthoor. lMEC Lab: J. Van Meerbergen, Philips Research Labs:H. DeMan, lMEC Lab:   .
6.2 A New Embedding Method for State Assignment,
    G. Saucier, C. Duff. INPG/CSI: F. Piorot, VLSI Technology
6.3 Finite State Machine Synthesis Using Shadow States,  .
    R. Graham, Silc Technologies
7.1 Viable Logic Synthesis Tools Using Transform Methods 
    D. Varma, E. A. Trachtenberg, Drexel University
7.2 Synthesis of Multilevel Networks with Simple Gates 
    X. Xiang. S. Muroga, University of Illinois
7.3 Logic Minimization for Factored Forms,
    A. Malik. R. Brayton, A. Sangiovanni-Vincentelli. University Of California-Berkeley
8.1 PLA-Based Synthesis Without PLA's,
     D. Brand, IBM Corp.
8.2 Technology Mapping for Delay,
     R. Rudell, Synopsys, lnc.
8.3 Redundancy Identification and Removal.
    D. Bryan, Microelectronics Center of North Carolina,
    F. Brglez, Microelectronics Center of North Carolina/BNR.,
    R. Lisanke. Microelectronics Center of North Carolina
9.1 Algorithms for State Assignments of Finite State Machines for Optimal Two-Level Logic implementations,
    T. Villa, A. Sangiovanni-Vincentelli, University of California-Berkeley
9.2 A Generalized PLA Decomposition with Programmable Encoders.
    S. Yang. M. Ciesielski, University of Massachusetts 
9.3 Encoding Symbolic Inputs for Multi-Level Logic implementation, 
    S. Malik, R. Brayton, A. Sangiovanni-Vincentelli, University of California-Berkeley
10.1 Computational Complexity of Logic Synthesis and Optimization, 
     K. Keutzer, AT&T Belt Laboratories:  D. Richards, University of Virginia
10.2  On the Complexity of Three-Level Logic Circuits, 
     T. Sasao, Kyushu Institute of Technology
11.1 Communication Complexity Driven Logic Synthesis,
     T-T Hwang. R. Owens. J. Irwin, Pennsylvania State University 
11.2 Min-Cut Algorithm for State Coding,
     N. Benschop. Philips Research Labs
11.3 Technology Mapping for Sequential Logic Synthesis.
   C.W. Moon, B. Lin. H. Savoj. R. Brayton. University of California-Berkeley