International Workshop on Logic Synthesis
          Research Triangle Park, North Carolina, USA
                 May 12-15, 1987
    Sponsored by the Microelectronics Center of North Carolina (MCNC)
       In Cooperation with the IEEE Circuits and Systems Society
               and the CANDE Committee of CAS


1.1 ''Business and Market Issues in Logic Synthesis,''
           Gary F. Hromadko, Robertson, Colman, & Stephens
1.2 ''The Present Status of Logic Synthesis in Japan,'
            Tsuneta Sudo, NTT
2.1 ''Algorithms for Multilevel Logic Minimization Based on Multilevel
   Tautology Checking/I G. Hachtel, R. Jacoby, C.R. Morrison, University of Colorado
2.2 ''MIS: A Multiple-level Logic Optimization System:'
      R. Brayton, IBM Corporation; R. Rudell,  A. Sangiovanni-Vincentelli, A.. Wang, 
2.3 ''Partitioning Before Logic Synthesis,'' R. Camposano, R. Brayton, IBM Corporation             .
3.1 ''HALMA: A Program for Logic Synthesis Considering Application-Specific Constraints, ''
       P. Pirsch,  A. Kemper, Technical University of Hannover       .
3.2 ''A Rule-based and Algorithmic Approach for Logic Synthesis,
         T. Yoshimura, S. Goto, NEC Corporation
3.3 ''Logic Optimization with Technology and Delay in Mind.. 
         J.F.M. Theeuwen, M.R.C.M. Berkelaar,      
4    Introduction of Logic Synthesis Benchmarks and Panel Discussion
          Aart de Deues.
5.1 ''Parallel Programming Approach to Minimization of Two-Level Networks with Negative Gates:
      M. Perkowski, Portland State University
5.2 ''An Automated multi-level Synthesis Methodology:'  
       K. Keutzer, M. Lega, M. Vancura, 
5.3 ''Technology Mapping in MIS,'' E. Detjens, University of California-Berkeley; G. Cannot, Intel
6.1 ''Synthesis interface Transducer Logic,'' G. Borriello, University of California
6.2 ''V-SYNTH: A VHDL Behavioral Synthesis System,'' ,
         S. Krolikoski, J. Bhasker, S. Natarajan, Honeywell
6.3 ''The Extraction and Meaning of Don't Cares in Hardware
          Description Language:' M. Lightner, G. Hachte1, D. Ravenscroft,
7.1 ''OPAL: A Multi-level Logic Optimization Tool:'
        G. Whitcomb, R. Newton, University of California-Berkeley
7.2 ''Efficient Algebraic Prime Factorization of Logic Expressions and Applications,'' 
     P. C. McGeer, University of California-Berkeley; R. Brayton, IBM Corporation  .
7.3 ''Testability Characterization of Embedded Modules Via Logic Minimization' 
    F. Brglez, Bell Northern Research
8.1 ''Logic Synthesis Techniques for PLA-based Control Functions,''
    C. Papachristou, A. Pandya, Case Western Reserve University
8.2 ''A Design Automation System for Spectral Logic Synthesis
      E.A. Trachtenberg, D. Varma, Drexel University 
8.3 ''A Timing-driven Logic Synthesis Environment;' 
     W.K. Chia, Y.F. Tsao, Y.M. Chou, LSI Logic Corporation
8.4 ''A Comprehensive Control Logic Layout Synthesis System' 
      C.H. Shaw, Texas Instruments
8.5 ''About Controlling Silicon Compilers Output,''
      A. Jerraya, N. Mhaya, B. Courtois, TIM3-IMAG/INPG
8.6 ''Behavioral Synthesis in ASP;'
      W.R. Bush, University of California-Berkeley
8.7 ''Area-timing Tradeoffs in Structural Synthesis,''
       G. De Micheli, Stanford University
8.8 ''A Behavioral Silicon Compiler Example' 
       J.H.G. Blank, Jeff Fox, Silc Technologies, Inc.
9.1 ''On State Machine Decomposition and the Five Primitives of Sequential Logic'
       N.F. Benschop, Philips Research Labs
9.2 ''Functional Decomposition of PLAs,'' 
     T. Sasao, Osaka University. 
9.3 ''New State Assignment Algorithms for Finite State Machines Using Counters and Multiple-PLA/ROM Structures,''
      R. Amann, U. Baitinger, University of Karlsruhe
10    Panel Discussion
      "Logic Synthesis: Present and Future,"
       Alberto Sangiovanni-Vincentelli