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Technical Program ULSI Workshop 1999

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Wednesday May 19, 1999 
10:20 - 10:30    Opening Remarks 
10:30 - 11:15    Invited Talk (1) 
Innovation of Intelligent Integrated Systems Architecture -Future Challenge,
 Michitaka Kamayama (Tohoku University, Japan)
11:15 - 12:00    Invited Talk (2) 
Quantum Electronic Circuit Concepts by Nanometric Technology, 
Hans Hartnagel (Technical University of Darmstadt, Germany)
12:00 - 13:00    Lunch 
13:00 - 14:20    Session 1: Nanoelectronics (4 Papers) 

1) High-Speed Single-Electron Memory and Logic, 
H. Mizuta, K. Tsukagoshi, K. Nakazato and H. Ahmed (Hitachi Cambridge, UK) 
2) Programmable HBT-Quantum Dot Structures for Arithmetic MVL, 
Lutz Micheel (Wright Lab., USA), A. Sigurdardottir, H. Hartnagel and K. Mutamba (Technical University of Darmstadt, Germany) 
3) GaAs- and InP-based Technologies of Resonant Tunneling Devices, 
O. Dupuis, P. Mounaix, F. Mollot, O. Vanbesien and D. Lippens (IEMN, France) 
4) Nano-Fabrication Technology and Silicon Nano-Devices, Toshio Baba (NEC, Japan)
14:20 - 14:40    Refreshment Break 
14:40 - 16:00    Session 2 : BDD/MDD (4 Papers) 

1) Nonapproximability Results for OBDD- and FBDD-Minimization, 
Detlef Sieling (University of Dortmund, Germany) 
2) Improving Reachability Analysis by means of Activity Profiles, 
Gianpiero Cabodi, Paolo Camurati and Stefano Quer (Politecnico di Torino, Italy) 
3) A Word-Level Graph Representation Package, 
Stefan Hoereth (Siemens, Germany) 
4) Interval Diagram Techniques and Their Applications, 
Karsten Strehl and Lothar Thiele (ETH Zuerich, Switzerland)

16:00 - 16:20    Refreshment Break 

16:20 - 17:40    Session 3: Application of Information Theory to Logic Design (4 papers) 

1) Information Theory Approach in Logic Design: Results, Trends and Non-Solved Problems, 
S. Yanushkevich (Poland/Belarus) and D. Simovici (USA), 
2) Methods of Information Engine Theory in Simple Examples, 
H. Watanabe (Japan) and S. Yanushkevich (Poland/Belarus), 
3) Information Measure in Evolvable Algorithm for Synthesis of Combinational Circuits, 
C. Moraga (Germany), J. Kolodziejczyk (Poland), M. Opoka (Poland) and S. Yanushkevich (Poland/Belarus), 
4) Information Theoretical Approach in Reed-Muller Expansion Minimization, 
D. Popel (Belarus), Shmerko (Poland/Belarus), S.Yanushkevich (Poland/Belarus)