--------------------- PROGRAM(tentative) -------------------------
                   7th International Workshop on 
        Post-Binary Ultra-Large-Scale Integration Systems
                  Fukuoka Software Research Park
                       Fukuoka, Japan
                       May 26, 1998
 
                        [ Tutorial ]
                         10:00--11:00
     Chair: D. A. Simovici (University of Boston, USA)

            <<< presentation tile is now considering >>>
     S. Rudeanu, (University of Bucharest, Rumania)
 
                      (10-minute break)
 
                      [General sessions]
 
 ------------------------[Session 1]---------------------------
                        11:10--12:30
     Challenging of Multiple-Valued VLSI Circuits and Devices

     Chair: T. Hanyu (Tohoku University, Japan)

     11:10--11:30
     T. Waho (NTT Lab., Japan)
     10-GHz Multiple-Valued Circuits Using Resonant-Tunneling Devices

     11:30--11:50
     P. G. Gulak (Univ. of Toronto, Canada)
     CMOS Field-Programmable Analog and Mixed Signal Arrays

     11:50--12:10
     S. Kawahito (Toyohashi Univ. of Tech., Japan)
     A Mixed Sensor, Analog and Digital Architecture for 
     a Post-Binary System LSI. 

     12:10--12:30
     Y. Yuminaka (Gunma Univ., Japan)
     Wave-Parallel Computing Paradigm Based on Multiplexing of Signals

                       (Lunch break)
 
 ------------------------[Session 2]---------------------------
                        13:30--14:30
              Special Issue on BDD/MDD --Part 1--

    Chair: T. Sasao (Kyushu Institute of Tech., Japan)

    13:30--13:50
    H. Sawada, S. Yamashita and A. Nagoya
    (NTT Communication Science Laboratories, Japan)
    Efficient Methods for a Simple Disjoint Decomposition 
    and a Non-Disjoint Bi-Decomposition

    13:50--14:10
    H. Higuchi and Y. Matsunaga
    (Fujitsu Laboratories Ltd., Japan)
    Improving the Efficienty of Symbolic FSM Traversal 
    by Dynamic Removal of Flip-Flops
 
                      (15-minute break)
 
 ------------------------[Session 3]---------------------------
                        14:25--15:25
              Special Issue on BDD/MDD --Part 2--
     Chair: R. Drechsler (Albert-Ludwigs-University, Germany)

     14:25--14:45
     Masaki Nakanishi, Kiyoharu Hamaguchi, Toshinobu Kashiwabara
     (Oosaka University, Japan)
     An Exponential Lower Bound on the Size of a Binary Moment Diagram
     Representing Division

     14:45--15:05
     B. Becker (Germany)
     Word-level Decision Diagrams in Verification

     15:05--15:25
     E. Dubrova (Royal Institute of Technology, Sweden)
     On Dependable Strategy for Dynamic Reordering Algorithms
 
                      (15-minute break)
 
 ------------------------[Session 4]---------------------------
                        15:40--17:00
           Testing in Multiple-Valued Logic Networks
     Chair: V. P. Shmerko (Technical University of 
            Szczecin, Poland)

     15:40--16:00
     R. Drechsler (Germany), V. Levashenko (Belarus), A. Shakirin 
     (Belarus), S. Yanushkevich (Poland/Belarus).
     Genetic Test Pattern Generation for MVL Combinational 
     Circuits 
    
     16:00--16:20
     G. Holowinski (Poland), V. Levashenko (Belarus), C. Moraga 
     (Germany), S.Yanushkevich (Poland/Belarus).
     Some New Results of Experiments on Testing MVL Combinational 
     Circuits with the Generalized D- algorithm. 

     16:20--16:40
     Ugur Kalay, Douglas Hall, and Marek Perkowski (Portland 
     State University),
     Minimal Universal Test Set for Single Faults 
     in Galois-Sum-of-Products Circuits.

     16:40--17:00
     V. Shmerko (Poland/Belarus), S. Jaroszewicz (Poland), 
     D. Simovici (USA), 
     V.Cheushev (Belarus). Four Remarks on Minimization of Strongly 
     Unspecified Logic function 
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