Advance Program

The 28th International Symposium on Multiple-Valued Logic
       Software Research Park(SPR)*, Fukuoka, Japan
 (* The Banquet is held in the Sea Hawk Hotel and Resort) 

Tuesday, May 26

10:00-17:30 7th International Workshop on Post-Binary
            ULSI Systems (Room A)

17:30-18:00 Registration

18:00-20:00 Reception (Room B)  

Wednesday, May 27

8:00-8:30 Registration 

8:30-8:45 Opening Remarks (Room A)

8:45-9:30 Session I(Room A): Invited Address 
Chair: M. Kameyama (Tohoku Univ., Japan)

       T. Okuda (NEC, Japan)
       Advanced Circuit Technology to Realize Post Giga-bit DRAM

9:30-9:50 Coffee Break

9:50-11:05 Session IIa (Room A): Devices
Chair: K. C. Smith (Hong Kong Univ. of Science and Tech., China)

       T. Baba and T. Uemura (NEC, Japan)
       Development of InGaAs-Based Multiple-Junction Surface
       Tunnel Transistors for Multiple-Valued Logic Circuits 

       T. Itoh, T. Waho, K. Maezawa and M. Yamamoto (NTT System 
       Electronics Lab., Japan)
       Ultrafast Ternary Quantizer Using Resonant Tunneling
       M. Morisue, J. Endo, T. Morooka and N. Shimizu (Hiroshima 
       City Univ., Japan)
       A Josephson Ternary Memory Circuit 

9:50-11:05 Session IIb( Room B): Cellular Array and Fault Tolerance
Chair: C. Moraga (Univ. of Dortmund, Germany)

       I. Takanami (Iwate Univ., Japan) 
       A Note on Realizing Multiple-Valued Logic Functions
       using Akers' Cells - Cell Sizes and Path Lengths -  
       N. Song and M. Perkowski (Portland State Univ., USA)
       Minimization of Exclusive Sums of Multi-Valued Complex 
       Terms for Logic Cell Arrays

       Y. Nagata(Univ. of the Ryukyus,Japan), D. M. Miller 
       (Univ. of Victoria, Canada) and M. Mukaidono(Meiji Univ.,Japan)
       Minimal Test Set Generation for Fault Diagnosis in R-Valued

11:05-11:15 Break

11:15-12:30 Session IIIa(Room A): Decision Diagrams 
Chair: Y. Matsunaga(Fujitsu Lab., Japan)

       H. M. Hasan Babu and T. Sasao (Kyushu Inst. of Tech.,Japan)
       Design of Multiple-Output Networks Using Time Domain 
       Multiplexing and Shared Multi-Terminal Multiple-Valued 
       Decision Diagrams 

       M. Miller (Univ. of Victoria, Canada)and R. Drechsler
       (Albert-Ludwigs-Univ., Germany)
       Implementing a Multiple-Valued Decision Diagram Package

       L. Macchiarulo and P. Civera (Politecnico di Torino, Italy)
       Ternary Decision Diagrams with Inverted Edges and Cofactoring
       - an Application to Discrete Neural Networks Synthesis 

11:15-12:30 Session IIIb(Room B):Algebra 1
Chair: T. Hikita (Meiji Univ., Japan)

       H. M. Chung, S. Y. Pi (Catholic Univ. of DaeguHyosung, Korea)
       and S. Rey (Catholic Univ. of Lille, France)
       The MacLaurin's and Taylor's Series Expansions 
       of the Symbolic Multiple Valued Logic Functions          

       N. Takagi, A. Hon-nami and K. Nakashima 
       (Toyama Pref. Univ., Japan)
       A Characterization of r-Valued Functions Monotonic in an
       Order Based on the Regularity 

       L. Renren (Xiangtan Univ., China)
       Some Results on the Decision for Sheffer Functions 
       in Partial K-Valued Logic(II)   

12:30-14:00 Lunch
12:30-14:00 TC Executive Subcommittee Meeting

14:00-15:15 Session IVa (Room A): Logic Design 1
Chair: M. Perkowski (Portland State Univ., USA)

       J. T. Butler (Naval Postgraduate School,USA)) and 
       T. Sasao (Kyushu Inst. of Tech., Japan)
       On the Properties of Multiple-Valued Functions that
       are Symmetric in Both Variable Values and Labels

       C. Moraga and W. Wang(Univ. of Dortmund, Germany)
       Evolutionary Methods in the Design of Quaternary Digital Circuits
       P. Lindgren (Lulea Univ. Sweden), R. Drechsler and B. Becker
       (Albert-Ludwigs-Univ., Germany)
       Look-up Table FPGA Synthesis from Minimized Multi-Valued Pseudo
       Kronecker Expressions

14:00-15:15 Session IVb(Room B): Logic
Chair: A. Nakamura (Meiji Univ., Japan)

       R. J. Bignall and M. Spinks (Monash Univ., Australia)
       Multiple-Valued Logics for Theorem-Proving
       in First Order Logic with Equality
       M. Baaz and R. Zach (Technical Univ. Vienna, Austria)
       Compact Propositional Goedel Logics 

       S. Akama (Teikyo Heisei Univ., Japan) and J. M. Abe 
       (Univ. of Sao Paulo, Brazil)
       Many-Valued and Annotated Modal Logics  

15:15-15:25 Coffee Break

15:25-16:10 Session V(Room A): Invited Address 
Chair: H. Yasuura (Kyushu Univ., Japan)

       Z. G. Vranesic (Univ. of Toronto, Canada)
       The FPGA Challenge

16:10-16:30 Break

16:30-18:10 Session VIa(Room A): VLSI Circuits 1
Chair: S. Kawahito (Toyohashi Inst. of Tech., Japan)

       J. Shen, K. Tanno, O. Ishizuka and Z. Tang 
       (Miyazaki Univ., Japan)
       Application of Neuron-MOS to Current-Mode
       Multi-Valued Logic Circuits 

       T. Hanyu, T. Saito, and M. Kameyama (Tohoku Univ., Japan)
       Asynchronous Multiple-Valued VLSI System Based on Dual-Rail
       Current-Mode Differential Logic

       T. Aoki and T. Higuchi (Tohoku Univ., Japan)
       Set-Valued Logic Circuits for Next Generation
       VLSI Architectures

       Y. Yuminaka, Y. Sasaki(Gunma Univ., Japan), T. Aoki and T. Higuchi 
       (Tohoku Univ., Japan)
       Wave-Parallel Computing Systems Using Multiple-Valued 
       Pseudo-Orthogonal Sequences

16:30-18:10 Session VIb(Room B): Applications of Multiple-Valued Logic
Chair: M. Mukaidono(Meiji Univ.,Japan)

       Y. Hata, M. Ishikawa (Ishikawa Hospital, Japan) and 
       N. Kamiura (Himeji Inst. of Tech., Japan)
       Image Segmentation Based on Kleene Algebra 
       A. Ngom (Univ. of Ottawa, Canada), C. Reischer (Univ. of Quebec, Canada), 
       D. Simovici (Univ. of Mass., USA) and I. Stojmenovic
      (Univ. of Ottawa, Canada)
       Learning with Permutably Homogeneous Multiple-Valued
       Multiple-Threshold Perceptrons

       C. Files and M. Perkowski (Portland State Univ., USA)
       An Error Reducing Approach to Machine Learning Using 
       Multi-Valued Functional Decomposition

       C. Files and M. Perkowski (Portland Sate Univ., USA)
       Multi-Valued Functional Decomposition as a Machine Learning Method

Thursday, May 28

8:00-8:30 Registration

8:30-9:45 Session VIIa(Room A):  Logic Design 2
Chair: D. M. Miller (Univ. of Victoria, Canada)
       B. J. Falkowski (Nanyang Technological Univ., Singapore)
       Fast Multi-Polarity Complex Hadamard Transform
       for Logic Functions 

       R. Stankovic, D. Jankovic (Univ. of Nis, Yugoslavia) and 
       C. Moraga (Univ. of Dortmund, Germany)
       Reed-Muller-Fourier Versus Galois Field
       Representations of Four-Valued Logic 

       L. J. Thaden (USA)
       Constructing an MVL Patterned After Boolean Logic       

8:30-9:45 Session VIIb(Room B): Genetic Algorithms in MVL  
Chair: T. Nagata (ISIT, Japan)

       Y. Yamamoto (Takasaki City Univ. of Economics, Japan)
       A Synthesis Method of the Approximate Reasoning Engine 
       by means of Genetic Algorithm 

       A. Ngom,  Z. Obradovic, I. Stojmenovic (Univ. of Ottawa, Canada)
       Minimization of Multivalued Perceptrons using Genetic Algorithms    
       M. Keim, N. Goeckel, R. Drechsler, B. Becker
       (Albert-Ludwigs-Univ., Germany)
       Test Generation for (Sequential) Multi-Valued Logic Networks 
       based on Genetic Algorithm

9:45-9:55 Break

9:55-10:40 Session VIII(Room A): Invited Address
Chair: M. Morisue (Hiroshima City Univ., Japan)

       P. G. Gulak (Univ. of Toronto, Canada)
       A Review of Multiple-Valued Memory Technology

10:40-11:00 Coffee Break

11:00-12:15 Session IXa(Room A): Minimization
Chair: K. Yamato (Fukuoka Inst. of Tech., Japan)

       T. Hozumi, O. Kakusho (Hyogo Univ., Japan)
       and Y. Hata (Himeji Inst. of Tech., Japan)
       On Low Cost Realization of Multiple-Valued Logic Functions 

       B. Fraser and G. W. Dueck (St. Francis Xavier Univ., Canada)
       Multiple-Valued Logic Minimization using Universal Literals
       and Cost Tables

       M. H. Abd-El-Barr and M. Abd-El-Barr(King Fahd Univ.
       of Petroleum and Minerals, Saudi Arabia)
       A Frontier Algorithm for Optimization 
       of Multiple-Valued Logic Functions 

11:00-12:15 Session IXb(Room B): Algebra 2
Chair: I. Stojmenovic (Univ. of Ottawa, Canada)

       G. R. Pogosyan and T. Nakamura (International Christian
       Univ., Japan)
       e-Bases of Triadic Logic Operations

       V. Cheushev (State Univ., Minsk, Belarus),
       V. Shmerko (Technical Univ., Szczecin, Poland),
       D. A. Simovici (Univ. of Massachusetts at Boston, USA) and
       S. Yanushkevich (Technical Univ., Szczecin, Poland)
       Functional Entropy and Decision Trees

       G. Epstein (USA)
       B-algebra and Associated Logics

12:15-13:45 Lunch

12:15-13:45 Symposium Subcommittee Meeting

13:45-15:25: Session Xa(Room A): VLSI Circuits 2
Chair: F. Ueno (Kumamoto National College of Tech., Japan)

       A. Sheikholeslami (Univ. of Toronto, Canada),
       R. Yoshimura(Osaka Univ. Japan)
       and P. G. Gulak (Univ. of Toronto, Canada)
       Look-up Tables(LUTs) for Multiple-Valued, Combinational Logic
       T. Hanyu, K. Teranishi, and M. Kameyama 
       (Tohoku Univ., Japan)
       Multiple-Valued Floating-Gate-MOS Pass Logic and Its 
       Application to Logic-in-Memory VLSI
       S. Wei and K. Shimizu (Gunma Univ., Japan)
       Residue Arithmetic Circuits Based on the Signed-Digit
       Multiple-Valued Arithmetic Circuits 

       K. Shimabukuro and C. Zukeran (Univ. of the Ryukyus, Japan)
       Reconfigurable Current-Mode Multiple-Valued
       Residue Arithmetic Circuits

13:45-15:25: Session Xb(Room B): Theory of Fuzzy Logic
Chair: N. Nakajima (Toyama Univ., Japan)

       T. Araki, H. Tatsumi (Kanagawa Inst. of Tech., Japan),
       M. Mukaidono(Meiji Univ.,Japan)
       and F. Yamamoto (Kanagawa Inst. of Tech., Japan)
       Minimization of Incompletely Specified Regular Ternary
       Logic functions and its Application to Fuzzy Switching

       H. Tatsumi, T. Araki (Kanagawa Inst. of Tech., Japan),
       M. Mukaidono (Meiji Univ.,Japan)
       and S. Tokumasu (Kanagawa Inst. of Tech., Japan)
       Upper and Lower Bounds on the Number of Fuzzy/C
       Switching Functions

       H. Thiele(Univ. of Dortmund, Germany)
       On Closure Operators in Fuzzy Deductive Systems and Fuzzy Algebras

       Y. Yamauchi(International Christian Univ., Japan) 
       and M. Mukaidono (Meiji Univ., Japan)
       A Study on Operations in Interval and Paired Probabilities 

15:25-15:45 Coffee Break

15:45-16:30 Session XI(Room A): Invited Address 
Chair: D. Simovici (Univ. of Massachusetts at Boston, USA)

       T. Shibata (Univ. of Tokyo, Japan)
       Functional-Device-Based VLSI for Intelligent Electronic Systems

16:30-17:30 Plenary Session(Room A)

18:30-20:30 Banquet (Sea Hawk Hotel and Resort: NAVI Room)

Friday, May 29

8:00-8:30 Registration

8:30-9:15 Session XII(Room A): Invited Address
Chair: A. Nozaki (Otsuma Women's Univ., Japan)

       I. G. Rosenberg (Univ. of Montreal, Canada)
       Multiple-Valued Hyperstructures

9:25-10:10 Session XIII(Room A): Invited Address
Chair: R. Hahnle (Univ. of Karlsruhe, Germany)

       T. Yamakawa (Kyushu Inst. of Tech., Japan)
       A Novel Nonlinear Synapse Neuron Model Guaranteeing
       a Global Minimum  --Wavelet Neuron --

10:10-10:30  Coffee Break

10:30-12:00 Session XIVa(Room A): Applications of Fuzzy Logic
Chair: Y. Koga(National Defense Academy, Japan)

       C. Kahraman (Istanbul Technical Univ., Turkey) 
       and E. Tolga (Galatasaray Univ., Turkey)
       Data Envelopment Analysis using Fuzzy Concept

       F. Wakui and M. Hirano (Nihon Univ., Japan) 
       A Proposal and an Application of a Career Mode
       Membership Function 

       M. Tokumaru, K. Yamashita, N. Muranaka and S. Imanishi 
       (Kansai Univ., Japan)
       Membership Functions in Automatic Harmonization System 

       N. Kamiura, Y. Hata(Himeji Inst. of Tech., Japan) and
       K.Yamato(Fukuoka Inst. of Tech., Japan)
       On Concurrent Tests of Fuzzy Controllers 

10:30-12:00 Session XIVb(Room B): Clone Theory
Chair: M. Miyakawa(Tsukuba College of Tech., Japan)

       L. Haddad and F. Borner (Royal Military College, Canada)
       Generating Sets for Clones and Partial Clones

       J. Fugere and L. Haddad (Royal Military College, Canada)
       On Partial Clones Containing All Partial Idempotent Operations

       H. Machida (Hitotsubashi Univ., Japan)
       Some Continuous Maps on the Space of Clones in Multiple-Valued Logic

       A. Nozaki (Otsuma Women's Univ., Japan) 
       and V. Lashkia (Okayama Univ. of Science, Japan) 
       A Finite Basis of the Set of All Monotone Partial
       Functions Defined over a Finite Poset  

13:20-15:00 Technical Visit
            Matsushita Gruop,
            Fujitsu Laboratories