Preliminary Program =================== Monday, May 24 18:00-19:00 Registration 19:00-21:00 Reception Tuesday, May 25 8:00-8:15 Opening Remarks Wayne Current or any dignitaries like the Mayor of Sacramento or the Governor of California 8:15-9:15 Session 1: Invited Address D. M. Miller 9:15-9:45 Refreshments Break 9:45-11:25 Session 2a: Logic Minimization AS06Fast Synthesis for Ternary Reed-Muller Expansion , Qinhua Hong, Benchu Fei (Ningbo University, China) and Haomin Wu (Portland State University, U.S.A) AM09Multiple-Valued Programmable Logic Arrays Minimization by Concurrent Multiple and Mixed Simulated Annealing, Cem Yildrirm, Jon T. Butler (Naval Postgraduate School), and Chyan Yang (National Chiao Tung University) EA04Entropic Minimization of Multi-Valued Functions, Antonio Lloris- Ruiz, Juan Francisco Gomez-Lopera and Ramon Roman-Roldan (Universidad de Grenada, Spain) AS12Gate Model Networks for Minimization of Multiple-Valued Logic Functions, Yutaka Hata, Takahiro Hozumi and Kazuharu Yamato (Himeji Institute of Technology, Japan) 9:45-11:25 Session 2b: Logic AS02A Canonical Disjunctive Form of Extended Kleene-Stone Logic Function , Noboru Takagi, Kyoichi Nakashima (Toyama Prefectural University, Japan) and Masao Mukaidono (Meiji University, Japan) AS16Three-Valued Nonmonotonic Logic, Zuoquan Lin (Shantou University, China) AM10Signed Formulas and Annotated Logics, James J. Lu (Bucknell University), Neil V. Murray (State University of NY), and Erik Rosenthal (University of New Haven) AM08Minimal Resolution Proof Systems for Finitely-Valued Lukasiewicz Logics, E. Harley and Z. Stachniak (York University) 11:25-14:00 Lunch and Executive Subcommittee Meeting 14:00-15:10 Session 3a: Fuzzy Logic EA07On the definition of modal operators in fuzzy logic, Helmut Thiele (University of Dortmund, Germany) AS17Single-Chip Realization of a Fuzzy Logic Controller with Neural Network Structure (NNFLC), Wang Zhenfeng, Jin Dongming and Li Zhijian (Tsinghua University, China) AM19Synthesis and Design Automation of Analog Fuzzy Logic VLSI Circuits, Laurent Lemaitre, Marek J. Patyra, and Daniel Mlynek (Swiss Federal Institute of Technology) 14:00-15:10 Session 3b: Algebra I AM01On Functional Entropy, Dan A. Simovici (University of Massachusetts) and Corina Reischer (University of Quebec) AS09Semirigid Sets of Clones of Quasi-Linear Functions over a Finite Domain, Akihiro Nozaki, Grant Pogosyan (International Christian University, Japan) Masahiro Miyakawa (Tsukuba College of Technology, Japan) and Ivo G. Rosenberg (Universite de Montreal) AS01Some Results on the Decision and Construction for Sheffer Functions in Partial K-Valued Logic , Liu Renren (Xiangtan University, China) 15:10-15:30 Refreshments Break 15:30-16:40 Session 4a: Testing AM21Novel CMOS Scan Design for VLSI Testability, Haomin Wu (Portland State University), Nan Zhuang (Ningbo Normal College), and Marek Perkowski (Portland State University) AS10A Method of Test Pattern Generation for Multiple-Valued PLA's, Yasunori Nagata and Chushin Afuso (University of Ryukyus, Japan) AS14A Repairable and Diagnosable Cellular Array on Multiple-Valued Logic, Naotake Kamiura, Yutaka Hata and Kazuharu Yamato (Himeji Institute of Technology, Japan) 15:30-16:40 Session 4b: Function Decomposition and Minimization AM23A Fast Algorithm For the Disjunctive Decomposition of m-Valued Functions Part I: The Decomposition Algorithm, Sami B. Abugharbieh and Samuel Lee (University of Oklahoma) AM24A Fast Algorithm For the Disjunctive Decomposition of m-Valued Functions Part II: Time Complexity Analysis, Sami B. Abugharbieh and Samuel Lee (University of Oklahoma) AM20Exorcism-mv-2: Minimization of Exclusive Sum of Products Expressions for Multiple-Valued Input Incompletely Specified Functions, Ning Song and Marek Perkowski (Portland State University) Wednesday, May 26 8:15-8:15 Session 5: Invited Address Taksfumi Aoki 9:15-9:45 Refreshments Break 9:45-11:50 Session 6a: Circuits AS08Design and Examination of a Multiple-Valued Flip-Flop Circuit with Stair-Shaped I-V Curved Device as a Coupling Element, Shinji Karasawa (Miyagi National College of Technology, Japan) and Kazuhiko Yamanouchi (Tohoku University, Japan) AM07Series Resonant Tunneling Diodes as a Multiple-dimensional Memory Cell, Ming-Huei Shieh and Hung Chang Lin (University of Maryland) AM22Multiple-Valued Logic Computation Circuits using Micro- and Nanoelectronic Devices, Lutz J. Micheel (Wright Laboratory) and Albert H. Taddiken (Texas Instruments) AS19A Multiple-Valued Content-Addressable Memory Using Logic-Value Conversion and Threshold Functions, Satoshi Aragaki, Takahiro Hanyu and Tatsuo Higuchi (Tohoku University, Japan) AM26Multiple Valued Logic: Current-Mode CMOS Circuits, K. Wayne Current (University of California) 9:45-11:50 Session 6b: Learning and Reasoning AS13An Inference Engine of Approximate Reasoning with Analogy, Kiyotaka Miyai, Yutaka Hata and Kazuharu Yamato (Himeji Institute of Technology, Japan) AS25An Inexact Reasoning Technique Using Linguistic Rule Matrix Transformations, Shyi-Ming Chen (National Chiao Tung University, Taiwan) AS04Algebraic Properties of a Learning Multiple-Valued Logic Networks, Zheng Tang, Okihiko Ishizuka, Qi-xin Cao and Hiroki Matsumoto (Miyazaki University, Japan) AS05Algorithm and Implementation of a Learning Multiple-Valued Logic Networks, Qi-xin Cao, Okihiko Ishizuka, Zheng Tang and Hiroki Matsumoto (Miyazaki University, Japan) EA06Systematic Construction of Natural Deduction Systems for Many- Valued Logics, Matthias Baaz, Christian G. Fermuller, and Richard Zach (Technische Universitat Wien, Austria) 11:50-14:00 Lunch 14:00-15:35 Session 7a: Logic Design AM13A Basis for the Comparison of Binary and m-Valued Current Mode Circuits: the Multioperand Addition with Redundant Number Systems, D. Etiemble and K. Navi (Universite de Paris Sud) AS11Multiple-Valued Logic Functions Represented by TSUM, TPRODUCT, NOT and Variables, Yutaka Hata and Kazuharu Yamato (Himeji Institute of Technology, Japan) AM15Decimal Addition and Subtraction Units Using the p-Valued Decimal Signed-Digit Number Representation, Noriaki Murannaka, Shigeru Imanishi (Kansai University), and D. M. Miller (University of Victoria) 14:00-15:35 Session 7b: Special Applications AM25CMOS Implementation of a Pseudo Analog Neuron, Babak A. Taheri (SRI International) AS20Impact of Interconnection-Free Biomolecular Computing, Takafumi Aoki and Tatsuo Higuchi (Tohoku University, Japan) AS-21Design of Set-Valued Logic Networks for Wave-Parallel Computing, Yasushi Yuminaka, Takafumi Aoki and Tatsuo Higuchi (Tohoku University, Japan) AM18Design of Multiple-Valued Linear Digital Circuits for Highly Parallel Unary Operations, Masami Nakajima and Michitaka Kameyama (Tohoku University) 15:35-15:50 Refreshments Break 15:50-17:00 Plenary Session: MVL-TC Meeting 19:00-21:00 Banquet Thursday, May 27 8:15-8:15 Session 8: Invited Address Jonathan Mills 9:15-9:45 Refreshments Break 9:45-11:50 Session 9a: Algebra II AS07Calculation of Ternary Mixed Polarity Function Vectors, Qinhua Hong, Benchu Fei (Ningbo University, China) and Nan Zhuang (Ningbo Normal University, China) EA01An Algebra for Current-Mode CMOS Multivalued Circuits, Xiexiong Chen (Hongzhou University, PR China) and Claudio Moraga (University of Dortmund, Germany) AM12Current-Mode CMOS Galois Field Circuits, Zeljko Zilic and Zvonko Vranesic (University of Toronto) AM16Functional Completeness and Weak Completeness in Set Logic, Dan A. Simovici (University of Massachusetts), Ivan Stomenovic (University of Ottawa), and Ratko Tosic (University of Novi Sad) 9:45-11:50 Session 9b: Stiquito Tutorial Jonathan Mills

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