MULTIPLE-VALUED LOGIC
                               Aoba Memorial Hall
                           Tohoku University, Aoba-ku
                               Sendai 980, Japan
                               May 27 -- 29, 1992
                                ADVANCE PROGRAM

     16:00-18:00 Registration  --  Lobby, Sendai Hotel
     18:30 Welcome Party  --  Cattleya Room, Sendai Hotel

      8:00-8:30 Registration 
      8:30-8:45 Opening Remarks
      8:45-9:30 Session I : Invited Address
       *  High-speed digital circuits for a Josephson computer,
       Shinya Hasuo (Fujitsu Laboratories Ltd.).

      9:30-9:50 Coffee Break
      9:50-11:05 Session IIa : Device-Based Circuit
       *  A superconducting ternary systolic array 
         Mititada Morisue and Fu-quiang Li (Saitama University).
       *  Heterojunction bipolar technology for 
         emitter-coupled multiple-valued logic in gigahertz adders and 
         Lutz J. Micheel (Wright Laboratory).
       *  Unique folding and hysteresis characteristics 
         of RTD for multi-valued logic and counting applications,
         Sen-Jung Wei and H. C. Lin (University of Maryland).

      9:50-11:05 Session IIb : Test
       *  Easily testable multiple-valued cellular arrays,
         Naotake Kamiura, Yutaka Hata, Fujio Miyawaki and Kazuharu Yamato 
         (Himeji Institute of Technology).
       *  Aliasing in multiple-valued test data compaction,
         Geetani Edirisooriya and John P. Robinson (The University of Iowa).
       *  A new balanced gate for structural testing,
         Hassan M. Razavi and  Paul W. Wong, (University of North Carolina at

     11:05-11:15 Break
     11:15-12:30 Session IIIa : Logic Minimization
       *  Direct cover MVL minimization with cost-tables,
         Gerhard W. Dueck (Naval Postgraduate School).
       *  Multiple-valued Programmable logic array 
         minimization by simulated annealing,
         Gerhard W. Dueck, Robert C. Earle, Jon T. Butler
         (Naval Postgraduate School) and
         Parthasarathy P. Tirumalai (Hewlett-Packard Laboratories).
       *  Experiences of parallel processing with direct 
         cover algorithms for multiple-valued logic minimization,
         Chyan Yang and Onur Oral (Naval Postgraduate School).

     11:15-12:30 Session IIIb : Neural Network
       *  Design of a 4-valued digital multiplier using 
         an artificial heterogeneous two-layered neural network,
         Chia-Lun J. Hu (Southern Illinois University).
       *  Layered MVL neural networks capable of
         recognizing translated characters,
         Tatsuki Watanabe and Masayuki Matsumoto (Toyo University).
       *  A deductive neural-logic system,
         Joo-Hwee Lim, Ho-Chung Lui and Hoon-Heng Teh (National University 
         of Singapore).
     12:30-14:00 Lunch
     14:00-15:15 Session IVa : Circuit Design

       *  Towards the realization of 4-valued CMOS 
         Konrad Lei and Zvonko G. Vranesic (University of Toronto).
       *  Incremental gate: A method to compute minimal 
         cost CCD realizations of MVL functions,
         M. Abd-El-Barr, H. Choy (University of Saskatchewan).
       *  The theory of clipping voltage-switches and 
         design of quaternary nMOS circuits,
         Xunwei Wu (Hangzhou University).

     14:00-15:15 Session IVb : Algebra I
       *  An application of the p-valued input 
         q-kind-valued output logic to the synthesis of the p-valued logical 
         Takahiro Haga (Aichi Institute of Technology).
       *  On the efficient decoding of Reed-Solomon codes
         based on GMD criterion,
         Kiyomichi Araki, Masayuki Takada (Saitama University) and 
         Masakatu Morii (Ehime University).
       *  NML3 -- A non-monotonic logic with explicit 
         Patrick Doherty (Link"oping University) and Witold Lukaszewicz
         (Institute of Informatics Warsaw University).

     15:15-15:35 Coffee Break
     15:35-16:20 Session V : Invited Address
       *  On the performance of multivalued integrated circuits: 
       past, present and future,
       Daniel Etiemble (Universite de Paris, Sud).

     16:20-16:30 Break
     16:30-17:45 Session VIa : Reliable System
       *  Concurrent checking and unidirectional errors 
         in multiple-valued circuits,
         David Wessels and Jon C. Muzio, (University of Victoria).
       *  Application of fail-safe multiple-valued logic to
         control of mechanical press,
         Masayoshi Sakai, Masakazu Kato (Nippon Signal Co. Ltd.) and 
         Masao Mukaidono (Meiji University).
       *  Fault analysis on two-level (k+1) valued logic 
         Chung Len Lee (National Chiao Tung University).

     16:30-17:45 Session VIb : Algebra II
       *  (n+1)-Valued modal implicative semilattices,
         M. C. Canals Frau and Aldo V. Figallo (Universidad Nacional De San 
       *  Multiplicative bases approach in multiple-valued 
         threshold logic,
         Sam L. Blyumin (Lipetsk Polytechnical Institute, Russia).
       *  Fuzzifying topological groups based on completely
         distributive residuated lattice-valued logic,
         Jizhong Shen (Jiangxi Normal University).

      8:00-8:30 Registration
      8:30-10:10 Session VIIa : Current-Mode Circuit
       *  Dynamic current-mode multi-valued MOS memory 
         with error correction,
         Edward K. F. Lee and P. Glenn Gulak (University of Toronto).
       *  Bi-CMOS current-mode multiple-valued logic 
         circuit with 1.5V supply voltage,
         Kazutaka Taniguchi (Yatsushiro National College of Technology) 
         Mamoru Sasaki, Yutaka Ogata and Fumio Ueno (Kumamoto University).
       *  On the synthesis of MVL functions for 
         current-mode CMOS circuit implementation,
         M. Abd-El-Barr and M. I. Mahroos (University of Saskatchewan).
       *  A current-mode CMOS algorithmic 
         analog-to-quaternary converter circuit,
         K. W. Current (University of California at Davis).

      8:30-10:10 Session VIIb : Algebra III
       *  On Multiple-valued logic functions monotonic 
         with respect to ambiguity,
         K. Nakashima and N. Takagi (Toyama Prefectural University, Japan).
       *  Fundamental properties of extended Kleene-Stone 
         logic functions,
         N. Takagi, K. Nakashima (Toyama Prefectural University) and 
         M. Mukaidono (Meiji University).
       *  On-set-valued functions and Boolean Collections,
         Ratko Tosic (University of Novi Sad), Ivan Stojmenovic (University
         of Ottawa), Dan A. Simovici (University of Massuchusettes-Boston)
         and Corina Reischer (University of Quebec).
       *  Rectangular algebras,
         R. P"oschel (Karl-Weierstra-Institut f"ur Mathematik) and 
         M. Reichel (University of Potsdam).

     10:10-10:30 Coffee Break
     10:30-11:15 Session VIII : Invited Address
       *  A universal logic machine, 
       Marek A. Perkowski (Portland State University) 

     11:15-12:15 Plenary Session
     12:15-13:30 Lunch
     13:30-14:45 Session IXa : VLSI I
       *  Design of a multiple-valued rule-programmable 
         Matching VLSI chip for real-time rule-based systems,
         Takahiro Hanyu, Kouichi Takeda and Tatsuo Higuchi (Tohoku 
       *  Set-valued logic networks based on optical 
         wavelength multiplexing,
         Shuichi Maeda, Takafumi Aoki and Tatsuo Higuchi (Tohoku University).
       *  Area-efficient implication circuits for very 
         dense Lukasiewicz logic arrays,
         Jonathan W. Mills (Indiana University).

     13:30-14:45 Session IXb : Completeness
       *  On semirigid sets of central clones over a finite
         Masahiro Miyakawa (Electrotechnical Laboratory), Akihiro Nozaki, 
         Grant Pogosyan (International Christian University) and
         Ivo G. Rosenberg (Universite de Montereal).
       *  Amplification of the functional closure 
         V. Lashkia (University of Electro-Communication).
       *  The completeness problem on the product of 
         algebras of finite-valued logic,
         B. A. Romov (Kiev Institute of Automation).

     14:45-15:05 Coffee Break
     15:05-15:50 Session X : Invited Address
       *  A Completeness criterion for semi-affine algebras,
       Agnes Szendrei; Bolyai Institute

     15:50-15:55 Break
     15:55-17:10 Session XIa : VLSI II
       *  Design of a multiple-valued VLSI processor for 
         digital control,
         Katsuhiko Shimabukuro, Michitaka Kameyama and Tatsuo Higuchi 
         (Tohoku University).
       *  Residue arithmetic based multiple-valued VLSI 
         image processor,
         Makoto Honda, Michitaka Kameyama and Tatsuo Higuchi (Tohoku
       *  Parallel hardware algorithms with redundant 
         number representations for multiple-valued arithmetic VLSI,
         S. Kawahito, Y. Mitsui, M. Ishida and T. Nakamura (Toyohashi 
         University of Technology).

     15:55-17:10 Session XIb : Spectral Technique
       *  Binary input/ternary output switching circuits 
         designed via the sign transformation,
         Ph. W. Besslich (University of Bremen) and E. A. Trachtenberg (Drexel
       *  Autocorrelation techniques for multi-bit decoder 
         R. Tomczuk and D. M. Miller (University of Victoria).
       *  Some remarks on Fourier transform and 
         differential operators for digital functions,
         Radomir S. Stankovic 

     18:30-20:30 Banquet
     20:00-20:25 Session XII : Special Session
       *  Profiles of topics and authors of the 
         international symposium on multiple-valued logic for 1971-1991,
         Susan W. Butler (Defense Manpower Data Center) and Jon T. Butler 
         (Naval Postgraduate School).

      8:00-8:30 Registration
      8:30-10:10 Session XIIIa : Logic Design
       *  Code Assignment algorithm for highly parallel 
         multiple-valued combinational circuits.
         Saneaki Tamaki, Michitaka Kameyama, and Tatsuo Higuchi (Tohoku 
       *  Optimal output assignment and the maximum number
         of implicants needed to cover the multiple-valued logic functions.,
         Yutaka Hata, Fujio Miyawaki and Kazuharu Yamato (Himeji Institute
         of Technology).
       *  On the use of multiple-valued switch-level 
         algebra to analyze binary MOS bridge circuits  and dynamic circuits,
         Mou Hu, Shensheng Xu, (Shanghai Institute of Railway Technology)
         and K.C. Smith (University of Toronto).
       *  Fast logic synthesis based upon ternary universal
         logic module Uf.,
         Benchu Fei (Ningbo University) and Nan Zhuang (Ningbo Normal 

      8:30-10:10 Session XIIIb : Fuzzy Logic I
       *   An automatic adjustment method of 
         backpropagation learning parameters, using fuzzy inference,
         Fumio Ueno, Takahiro Inoue, Badur-ul-Haque Baloch (Kumamoto 
         University) and Takayoshi Yamamoto (Kure works Babcock-Hitachi 
       *  A meaningful infinite-valued switching function
          --- Fuzzy threshold function and its application to process 
          control ---,
          Yoshinori Yamamoto (Takasaki City University of Economics).
       *  Inverted pendulum controlled circuit using fuzzy 
         state memory,
         Fumio Ueno, Takahiro Inoue, Motohiro Inoue, Kouji Tasaki (Kumamoto
         and Yuji Shirai (Yatsushiro National College of Technology).
       *  A propose of fault-checking fuzzy control,
         Hiroshi Ito, Takashi Matsubara, Takakazu Kurokawa and Yoshiaki
         Koga (National Defence Academy).

     10:10-10:20 Coffee Break
     10:20-11:35 Session XIVa : EXOR Synthesis
       *  Efficient derivation of Reed-Muller expansions in
         multiple-valued logic systems,
         B. Harking and C. Moraga (University of Dortmund).
       *  The generalized orthogonal expansion of functions
         with multiple-valued input and some of its applications,
         Marek A. Perkowski (Portland State University).
       *  Optimization of multiple-valued AND-EXOR 
         expressions using multiple-place decision diagrams,
         Tsutomu Sasao (Kyushu Institute of Technology).

     10:20-11:35 Session XIVb : Fuzzy Logic II
       *  On a logic based on fuzzy modalities,
         Akira Nakamura (Meiji University).
       *  Revision Principle for Approximate Reasoning -- 
         Based on Semantic Revising Method ---,
         Zuliang Shen, Liya Ding, Ho Chung Lui, Peizhuang Wang (National
         University of Singapore) and Masao Mukaidono (Meiji University).
       *  Converning ordered weighted averaging aggregation
         Heinz J. Skala (University of Paderborn, FRG).

     11:35-11:40 Break
     11:40-12:25 Session XV : Invited Address
       *  Fuzzy logic and the calculus of fuzzy if-then rules.,
         Lotfi A. Zadeh (University of California, Berkeley).

     12:25-12:35 Closing Remarks