30th IEEE International Symposium on Multiple-Valued-Logic 2000

Portland, Oregon
23-25 May 2000




Department of Electrical and Computer Engineering
Portland State University
Portland Center for Advanced Technology
1800 SW 6th.
Portland, Oregon, 97207-0751

Organizing Committee

Marek Perkowski, Symposium Chair
Malgorzata Chrzanowska-Jeske, Financial Chair
Xiayou Song, Publication Chair
W. Robert Daasch, Local Arrangement Chair

Department of Electrical and Computer Engineering
Portland State University,
Oregon, USA

Program Chairs

Dan Simovici, Program Chair Americas University of Masachussetts, Boston
Yutaka Hata, Program Chair Asia/Pacific Himeji Institute of Technology, Japan
Svetlana Yanushkevich, Program Chair Europe/Africa Technical University of Szczecin, Poland


We wish to thank the following institutions for their contribution to the success of this conference:
IEEE Computer Society.
Portland State University, Portland, Oregon.
Oregon Graduate Institute, Beaverton, Oregon.
Technical Committee on Multiple-Valued Logic.
Air Force Office of Scientific Research.
United States Air Force Research Laboratory.



Sunday, May 21
Full day excursion to Columbia Gorge, Mount Hood and Indian Reservation, including museum of Indian art.

Monday, May 22
LDL Workshop.
Conference registration
Welcome reception

Tuesday, May 23
Conference registration
Technical sessions of ISMVL 2000

Wednesday, May 24
Conference registration
Technical sessions of ISMVL 2000
Conference banquet in Pittock Mansion

Thursday May 25
Conference registration
Technical sessions of ISMVL 2000

Friday, May 26
ULSI Workshop

Saturday, May 27
Full day excursion to National Forests and Mount Saint Helens, the only living volcano in the continental USA


Tuesday, May 23

8:45 - 9:00     Opening remarks                     SMC Cascade Room
                Dan Bernsteine, 
                President, Portland State University
                Dan Hammerstrom, 
                Chair of ECE Department at Oregon Graduate Institute,
                M. Perkowski, Symposium Chair
Session 1:      Invited address                     SMC Cascade Room
Chair: Y. Hata
9:00 - 10:00   Computational Neurobiology Meets Semiconductor Engineering
               Dan Hammerstrom,
               Doug Strain Professor and Department Head,
               Electrical and Computer Engineering,
               Oregon Graduate Institute, USA
10:00 - 10:15  Refreshment break

Session 2a: Neural and Threshold Nets               SMC Cascade Room
Chair: J. Brzozowski
10:15 - 10:45   Multi-Valued Logic Pass
                Gate Network Using Neuron-MOS Transistors
                J. Shen, M. Inaba, K. Tanno, and O. Ishizuka
                Miyazaki University, Japan.

10:45 - 11:15   The Synthesis of the Multiple-Valued Logic
                Circuits Using the Local-Excitation-Type
                Neuron Models
                M. Matsumoto, Y. Ueda and I. Nomoto
                Toyo University, Japan.

11:15 - 11:45   Multi-Input Variable-Threshold Circuits for
                Multi-Valued Logic Functions
                M. Syuto, J. Shen, K. Tanno, and O. Ishizuka
                Miyazaki University, Japan.
11:45 - 12:15   The Computing Capacity of Three-Input 
                Multiple-Valued One-Threshold Perceptrons,
                A. Ngom, Lakehead University, Canada,
                I. Stojmenovic, University of Ottawa, Canada,
                R. Tosic, University of Novi Sad, Yugoslavia

Session 2b: Spectral Methods                    SMC Browsing Lounge
Chair: C. Moraga

10:15 - 10:45    MDD-based Synthesis of Multi-Valued Logic Networks
                R. Drechsler, Alberts-Ludwigs University, Germany, 
                M. Thornton, Missisipi State University, USA
                D. Wessels, University of Arkansas, USA

10:45 - 11:15    Fast Transforms for Multiple-Valued Input
                 Binary Output PLI Logic
                 B. J. Falkowski and S. Rahardja,
                 Nanyang Technological University, Singapore. 

11:15 - 11:45   Computation of Spectral Information
                from Logic Netlists
                R. Drechsler, Alberts-Ludwigs University, Germany, 
                M. A. Thornton, Mississippi State University, USA
11:45 - 12:15   Fault Analysis of the Multiple-Valued 
                Logic using Spectral Method
                J. O. Kim, Dongyang Technical College, Korea,
                P. Lala, University of Arkansas, USA,
                Y. G. Kim, Ansan College, Korea,
                and H. S. Kim, Inha University, Korea

12:15 - 13:30   Lunch Break (Executive Subcommittee Meeting) -  SMC Cascade Room.

Session 3: Invited Address                     SMC Cascade Room
Chair: B. Falkowski
13:30 - 14:30   Neural Networks: Binary Monotonic and Multiple-Valued
                J. Zurada, S.T. Fife Alumni Professor of
                Electrical and Computer Engineering, 
                University of Louisville, USA

14:30 - 14:45   Refreshment break

Session 4a: Decomposition and Data Mining          SMC Cascade Room
Chair: G. Dueck
14:45 - 15:15   Data Mining of Weak Functional Decomposition
                S. Jaroszewicz, and D. Simovici
                University of Massachusetts at Boston, USA

15:15 - 15:45   Multi-Valued Sub-functions Encoding
                in Functional Decomposition Based 
                on Information Relationships Measures
                A. Chojnacki, and L. Jozwiak,
                Eindhoven University of Technology,
                The Netherlands
15:45 - 16:15   On the Number of Dependent Variables for Incompletely
                Specified Multiple-Valued Functions
                T. Sasao, 
                Kyushu Institute of Technology, Japan
Session 4b: Algebra I                            SMC Browsing Lounge
Chair: M. Miyakawa

14:45 - 15:15   Some Properties of Discrete Interval Truth Values Logic
                N. Takagi and K. Nakashima,
                Toyama Prefectural University, Japan.

15:15 - 15:45   Independence of the Axioms of Boolean Algebra
                in Multiple-Valued Logic
                T. Ninomiya and M.Mukaidono,
                Meiji University, Japan
15:45 - 16:15   On Urguhart's C Logic
                A. Ciabattoni, 
                University of Milano, Italy.

16:15 - 16:30   Refreshment break

Session 5a: Fuzzy Logic                         SMC Cascade Room
Chair: M. Mukaidono 
16:30 - 17:00   A New Class of Fuzzy Modifiers
                M. DeCock, E. Kerre,  
                Universiteit Gent, Belgium

17:00 - 17:30   Fuzzy Decision Diagrams 
                for the Presentation of Rule Bases
                K. Strehl, Swiss Federal Institute of Technology,
                Switzerland, C. Moraga, and K.-H.Temme,
                Universitaet Dortmund, Germany,
                R. S. Stankovic, University of Nis, Yugoslavia

17:30 - 18:00   On Algebraic Formulation of Information Granulation III.
                Investigating the Hata-Mukaidono Approach
                H. Thiele, Universitaet Dortmund, Germany

Session 5b: Reed-Muller Logic                       SMC Browsing Lounge
            and Its Extensions 
Chair: J. Muzio
16:30 - 17:00    Experiments on FPRM Expressions for Partially Symmetric
                 Logic Functions,
                 S.N. Yanushkevich, Technical University of Szczecin, Poland,
                 J.T. Butler, Naval Postgraduate School, USA,
                 G. Dueck, University of New Brunswick, Canada,
                 V. Shmerko, Technical University of Szczecin, Poland

17:00 - 17:30    Representations of Multiple-Output
                 Switching Functions Using Multiple-Valued
                 Pseudo-Kronecker Decision Diagrams
                 H. M. H. Babu and T. Sasao,
                 Kyushu Institute of Technology, Japan.

17:30 - 18:00    A New Algorithm to Compute Quaternary
                 Reed-Muller Expansions
                 S. Rahardja and B.J. Falkowski,
                 Nanyang Technological University,

Wednesday, May 24

Session 6: Invited Address                      SMC Cascade Room
Chair: L. Jozwiak
 08:30 - 09:30  Evolvable Hardware: from on-chip circuit synthesis to
                Evolvable Space Systems
               A. Stoica, NASA, Pasadena, CA, USA.
09:30 - 09:45   Refreshment break

Session 7a: Logic and Algebra                     SMC Cascade Room
Chair: L. Haddad,
09:45 - 10:15    De Morgan Bisemilattices
                 J.A. Brzozowski, University of Waterloo, Canada

10:15 - 10:45    Finite-Valued Approximation of Product Logic  
                 S. Aguzzoli, Istituto per la Ricerca Scientifica
                 e Tecnologica,  Italy, 
                 B. Gerla, University of Milan, Italy

10:45 - 11:15    Integration of Information in Four-Valued Logics
                 under Non-Uniform Assumption
                 Y. Loyer, N. Spyratos, D. Stamate,
                 Laboratorie de Recherche en Informatique, France
Session 7b: Decision Diagrams                   SMC Browsing Lounge
Chair: M. Miller
09:45 - 10:15   Lower Bound Sifting for MDDs 
                D. Jankovic, University of Nis, Yugoslavia,
                W. Guenther, R. Drechsler,
                Albert-Ludwigs-University, Germany

10:15 - 10:45   Implementation of Multiple-Output Functions
                using PQMDDs 
                Y. Iguchi, Meiji University, Japan,
                T. Sasao, and M. Matsuura,
                Kyushu Institute of Technology, Japan,

10:45 - 11:15   Fibonacci Decision Diagrams 
                and Spectral Fibonacci Decision Diagrams  
                S. Stankovic, M. Stankovic,
                University of Nis, Yugoslavia
                J.T. Astola, K. Egiazarian, 
                Tampere Univ. of Technology, Tampere, Finland

11:15 - 11:30   Refreshment break

Session 8a: Circuits I                             SMC Cascade Room
Chair: M. Kameyama 

11:30 - 12:00   Cost-Analysis of 4-Valued Unary Functions 
                Implemented using Current-Mode CMOS Circuits
                M. Abd-El-Barr and A. Al-Mutawa,
                Kuwait University, Kuwait

12:00 - 12:30   Implementation of Multiple-Valued Multiplier on
                GF(3^m) using Current Mode CMOS
                H. K. Seong, Sangji University, Korea,
                J. S. Choi, Institute of Induk Technology, Korea,
                B. S. Shin, Ansan College, Korea, 
                and H. S. Kim, Inha University, Korea

12:30 - 13:00   Novel Pi-Type Resistor Network in D/A Converter
                based on multiple-valued logic
                X. Wu, Ningbo University, China,
                and X. Zhou, Center of Zhejiang University, China 

Session 8b: Decision Diagrams and Test             SMC Browsing Lounge
Chair: S. Yanushkevich
11:30 - 12:00   Mod-p Decision Diagrams:
                A Data Structure for Multiple-Valued Functions
                H. Sack, University of Trier, Germany,  
                E. Dubrova, Royal Institute of Technology, Sweden,
                Ch. Meinel, University of Trier, Germany

12:00 - 12:30   Dynamic Re-Encoding During MDD Minimization 
                F. Schmiedle, W. Guenther, R. Drechsler  
                Alberts-Ludwigs University, Germany  
12:30 - 13:00   Controllability/Observability Measures for Multiple-Valued Test
                Generation Based on D-algorithm
                N. Kamiura, Y. Hata, N. Matsui,
                Himeji Institute of Technology, Japan

13:00 - 14:15    Lunch Break                        Room

Session 9a: Evolutionary and Information 
Theory Approaches                                  SMC Cascade Room
Chair: O. Ishizuka

14:15 - 14:45    Evolutionary Multi-Level Network Synthesis
                 in Given Design Style
                 T. Luba, Techn. Univ. of Warsaw, Poland,
                 C. Moraga, Universitaet Dortmund, Germany,
                 S.N. Yanushkevich, M. Opoka, 
                 and V. Shmerko, Techn. Univ. Szczecin, Poland

14:45 - 15:15    An Evolutionary Computing Approach to
                 Multiple-Valued Logic Synthesis
                 Using Various Logic Operations
                 T. Hozumi, O. Kakusho and K.Yamato,
                 Hyogo University, Japan

15:15 - 15:45    Information Theoretic Approach to Mimimization
                 of Polynomial Expressions over GF(4)
                 S.N. Yanushkevich, D.V. Popel, V.P. Shmerko, Techn. Univ. Szczecin, Poland,
                 V.A. Cheushev, Belarussian State University, Belarus,
                 and R.S. Stankovic, University of Nis, Yugoslavia

Session 9b: Image and Language Processing                    SMC Browsing Lounge
Chair: D. Simovici

14:15 - 14:45   On the Architecture of Medical Image Registration System
                Based on Multiple-Valued Logic
                Y. Hata, S. Kobashi, N. Kamiura, Himeji Institute of Technology,
                Y. Kitamura, T. Yanagida, Osaka University Medical School, Japan

14:45 - 15:15   Gray Scale Image  Compression Based on
                Multiple-Valued Input Binary Functions, Walsh 
                and Reed-Muller Spectra
                B.J. Falkowski and L. S. Lim,
                Nanyang Technological University,

15:15 - 15:45   A Four-Valued Logic B(4) of E(9) for Modelling
                Human Communication
                D. Rine, and R. Alnakari,
                George Mason University, USA

15:45 - 16:00   Refreshment break

Session 10:  Invited Address                    SMC Cascade Room
Chair: X. Song
16:00 - 17:00   Structures with many-valued information
                and their relational proof theory.
                I. Duentsch, 
                W. MacCaull, 
                E. Orlowska,
                Institute of Telecommunications, Warsaw, Poland

17:00 - 18:00   Plenary Session                 SMC Cascade Room
                R. Haenhle, Chalmers University of Technology, Sweden

18:30           Banquet in Pittock Mansion
                Speaker: Prof. Wolf, Oregon Primate Research Center.
                Cloning and embryonic stem cells - implications to you and your health


Thursday, May 25

Session 11a: Circuits II                             SMC Cascade Room
Chair: T. Sasao
08:30 - 09:00    Demonstration of a Novel Multiple-Valued T-Gate using
                 Multiple-Junction Surface Tunnel Transistors 
                 and Its Application to Three-valued Data Flip-Flop
                 T. Uemura and T. Baba
                 NEC Corporation, Japan.

09:00 - 09:30    A Study on the Ternary Parallel Circuit
                 Design with DCG properties 
                 based on the Matrix Equation
                 G. N. Byun, C. U. Lee, S. Y. Park and H. S. Kim,
                 Inha University, Korea.
09:30 - 10:00    Novel Resonant-Tunneling Multiple-Threshold
                 Logic Circuit Based on Switching Sequence Detection
                 T. Waho, K. Hattori and K. Honda
                 Sophia University, Japan

10:00 - 10:30    Standard CMOS Implementation of a Multiple-Valued Logic
                 Signed-Digit Adder Based on Negative
                 Differential-Resistance Devices
                 A.G. Gonzalez, M. Bhattacharya, S. Kulkarni, 
                 and P. Mazumder, University of Michigan, USA

Session 11b:  Theorem-Proving and Applications                SMC Browsing Lounge
Chair: T. Hanyu

08:30 - 09:00    The 2-SAT Problem of Regular Signed CNF Formulas
                 B. Beckert, University of Karlsrue, Germany
                 R. Haenhle, Chalmers University of Technology, Sweden,
                 F. Manya, Universitat de Lleida, Spain  

09:00 - 09:30   Chaining Techniques for Automated Theorem Proving
                in Many-Valued Logics,
                H. Ganzinger,  V. Sofronie-Stokkermans, Max-Planck-Institut 
                fuer Informatik, Germany

09:30 - 10:00  High-Radix Parallel VLSI Dividers
               without Using Quotient Digit Selection Tables
               T. Aoki, K. Nakazawa and T. Higuchi
               Tohoku University, Japan.

10:30 - 10:45   Break

Session 12: Invited Address                          SMC Cascade Room
Chair: T. Aoki

10:45 - 11:45  Properties of Independent Components of Self-Motion
               Optical Flow
               Marvan Jabri,
               Gordon Moore Professor, Oregon Graduate Institute,
               Beaverton, USA,
               K.-Y. Park, S.-Y. Lee,
               and T. Sejnowski

Session 13: Panel Discussion                          SMC Cascade Room
Chair: D. Hammerstrom,

Panelists: D. Hammerstrom, E. Orlowska, M. Kameyama, R. Baltar, M. Jabri, 
M. Perkowski, D. Rine and Y. Takahashi

11:45 - 12:15   Multiple-Valued Logic: Provocative Questions.

Ten speakers will talk for 3 minutes each, trying to
answer as many as possible of these questions: 
- What is the definition of MVL as a research field?
- Give one application of MVL in everydays' life.
- How many MVL research groups exist in the world? 
- Are there regular MVL classes taught?
- Has any company done money on MVL-related products?
- If you are in industry: ``What is the industrial perception of MVL?''
- If you are in academia: ``What is the academic perception of MVL?''
- Is it possible to obtain grants for MVL research? Examples.
- If you want to teach somebody MVL, which book or other materials would you use?
- What is the single thing to be done to improve perception and usefulness of MVL?
12:15 - 13:30   Lunch break

Session 14: Invited Address                            SMC Cascade Room
Chair: S. Kulkarni

13:30 - 14:30    A Multilevel-Cell 32Mb Flash Memory
                 M. Bauer, R. Alexis, G. Atwood, Robert Baltar (presenter),
                 A. Fazio, K. Frary, M. Hensel, M. Ishac, J. Javanifard,
                 M. Landgraf, D. Leak, K. Loe, D. Mills, P. Ruby, R. Rozman,
                 S. Sweha, S. Talreja, K. Wojciechowski,
                 Intel Corporation, Folsom, CA, USA.

Session 15a: Circuits III                               SMC Cascade Room
Chair: T. Baba

14:30 - 15:00   Hardware Implementation of "Supplementary Symmetrical Logic
                Circuit Structure" Concepts
                Dan Olson, EDO LLC, USA,
                K.W. Current, K.W. Current Consulting, USA

15:00 - 15:30   Design of Quaternary Latch Circuit
                Using a Binary CMOS RS Latch, 
                K.W. Current, University of California, Davis, USA

15:30 - 16:00   Low-Power Dual-Rail Multiple-Valued Current-Mode
                Logic Circuit Using Multiple Input-Signal Levels
                T. Hanyu, T. Ike and M. Kameyama
                Tohoku University, Japan. 

Session 15b: Clones and Asynchronous Machines                           SMC Browsing Lounge
Chair: R. Haehnle

14:30 - 15:00   Rigidity problems of autodual clones
                M. Miyakawa, Tsukuba College of Technology, Japan,
                and I. G. Rosenberg, University of Montreal, Canada.

15:00 - 15:30   On the Intersection of Maximal Partial Clones 
                and the Join of Minimal Partial Clones
                L. Haddad, College Militaire Royal du Canada,
                H. Machida, Hitotsubashi University, Japan,
                I. G. Rosenberg, University of Montreal, Canada.

15:30 - 16:00   Logic Synthesis of Controllers 
                for B-ternary Asynchronous Systems,
                Y. Nagata, University of the Ryukyus, Japan,
                D. M. Miller, University of Victoria, Canada,
                M. Mukaidono, Meiji University, Japan

16:00 - 16:15   Refreshment break

Session 16: Invited Address                           SMC Cascade Room
Chair: T. Waho

16:15 - 17:15   Silicon Single-Electron Devices and their Applications
                Yasuo Takahashi, A. Fujiwara, Y. Ono, K. Murase,
                NTT Basic Research Laboratories, Japan

Session 17a: Arithmetics and Systems                   SMC Cascade Room
Chair: G. Gulak

17:15 - 17:45   Dram-Cell-Based Multiple-Valued
                Logic-in-Memory VLSI with Charge Addition
                and Charge Storage,
                T. Hanyu, H. Kimura and M. Kameyama
                Tohoku University, Japan 

17:45 - 18:15   An Efficient Data Transmission Technique 
                for VLSI Systems based on Multiple-Valued
                Code-Division Multiple Access
                Y. Yuminaka, O, Katoh, Y. Sasaki,
                Gunma University, Japan,
                T. Aoki, and T. Higuchi,
                Tohoku University, Japan
18:15 - 18:45   Arithmetic-Oriented Multiple-Valued Logic-in-Memory
                VLSI Based on Current-Mode Logic
                S. Kaeriyama, T. Hanyu and M. Kameyama
                Tohoku University, Japan. 

Session 17b: Verification and Power Estimation              SMC Browsing Lounge
Chair: G. Pogosyan

17:15 - 17:45   A Method for Approximate Equivalence Checking
                M. Thornton, Mississippi State University, USA
                R. Drechsler, W. Guenther,
                Alberts-Ludwigs University, Germany  

17:45 - 18:15   Propagation algorithm of behavior probability in
                power estimation based on multiple-valued logic
                X. Wu, Ningbo University, China, and M. Pedram, 
                University of Southern California, USA
18:15 - 18:45   Probabilistic verification 
                of Multiple-Valued Functions
                E. Dubrova,  Royal Institute of Technology,
                Sweden, and Harald Sack, University of Trier, Germany  

18:45 - 19:00   Closing remarks                          SMC Cascade Room