Logic Synthesis and Verification

Editors: S. Hassoun and T. Sasao
Consulting Editor: R. Brayton

1. Two-Level Logic Minimization
     O. Coudert and T. Sasao
2. Multi-Level Logic Optimization
     M. Fujita, Y. Matsunaga, and M. Ciesielski
3. Flexibility in Logic
     E. Sentovich and D. Brand
4. Multiple-Valued Logic Synthesis and Optimization
     E. Dubrova
5. Technology Mapping
     L. Stok and V. Tiwari
6. Technology-based Transformations
     R. Murgai
7. Logical and Physical Design
     O. Coudert
8. Logic Synthesis For Low Power
     L. Benini and G. De Micheli
9. Optimizations of Synchronous Circuits
     S. Hassoun and T. Villa
10. Asynchronous Control Circuits
     L. Lavango and S. Nowick
11. Ordered Binary Decision Diagrams
      R. Bryant and C. Meinel
12. SAT and ATPG: Algorithms for Boolean Decision Problems
      W. Kunz, J. Silva and S. Malik
13. Combinational and Sequential Equivalence Checking
     A. Kuehlmann and Koen van Eijk
14. Static Timing Analysis
     Y. Kukimoto, M. Berkelaar and K. Sakallah
15. The Future of Logic Synthesis and Verification
     R. Brayton