This book consists of fifteen chapters covering essential topics in
logic synthesis and verification. Each chapter presents key
developments,outlines future challenges, and lists essential references.
Two unique features of this book are technical strength and
comprehensiveness. The book chapters are written by twenty-eight
recognized leaders in the field and reviewed by equally qualified
experts. The topics collectively span the field. Certainly, it would
not have been possible for only one or two people to author all
the material in this book.
The topics covered are: two-level and multi-level logic minimization; flexibility in logic; and multiple-valued logic; technology mapping; technology-based transformations; logical and physical design from a flow perspective; logic synthesis for low power, optimizations of synchronous and asynchronous circuits, Ordered Binary Decision Diagrams, SAT and ATPG techniques, sequential and combinational equivalence checking, and static timing analysis. Future challenges in synthesis and verification are outlined throughout the chapters and collectively in an inspirational chapter at the end of the book.