About the Authors
Luca Benini received Ph.D. degree in
electrical engineering from Stanford University in 1997.
Since 1998 he has been an assistant professor in the department of
electronics and computer science in the University of Bologna.
He also holds visiting researcher positions at Stanford University
and the Hewlett-Packard Laboratories, Palo Alto, CA.
Dr. Benini's research interests are in all aspects of computer-aided
design of digital circuits, with special emphasis on low-power applications,
and in the design of portable systems. On these topics he has published
more than 120 papers in international journals and conferences, a book,
and several book chapters.
He is a member of the organizing committee of the International Symposium on
Low Power Design. He is a member of the technical program committee for several
technical conferences, including the Design and Test in Europe Conference,
International Symposium on Low Power Design, the Symposium on
received his M.E. and Ph.D. degrees in Electrical
Engineering from Eindhoven University of Technology, Eindhoven, the
Netherlands in 1987 and 1992, respectively. From 1992 to 2000, he was an
assistant and later associate professor of the Design Automation Section
of the department of Electrical Engineering of the Eindhoven University
of Technology. In 1994 and 1995 he spent a sabbatical year at IBM's T.J.
Watson Research Center, Yorktown Heights, NY. Since 2000, he is director
of the European Research Center of Magma Design Automation in Eindhoven,
the Netherlands. His research areas include logic synthesis, timing
analysis and optimization. He has published more than 40 papers on these
and related subjects. He served as the program chair for the
International Workshop on Logic Synthesis (IWLS) 2000 and several times
as topic chair for logic synthesis for the Design Automation and Test
Europe Conference (DATE).
Daniel Brand received the B.Sc., M.Sc., and Ph.D.
degrees in Computer Science
from the University of Toronto, Ontario, Canada, in 1972, 1973, and 1976,
He has held faculty/research positions at IBM Zurich Research Laboratory,
Beijing Institute of Aeronautics and Astronautics and
Kyushu Institute of Technology.
Now, he is a Research Staff Member at the IBM T. J. Watson Research Center,
Yorktown Heights, NY.
His research areas include logic optimization, performance analysis, and
hardware and software reliability.
He is a Fellow of the IEEE.
Robert Brayton received the BSEE degree from Iowa State University in 1956 and the Ph.D. degree in mathematics from MIT in 1961.
From 1961 to 1987 he was a member of the Mathematical Sciences Department
of the IBM T. J. Watson Research Center. In 1987 he joined the
EECS Department at Berkeley, where he is the Cadence Distinguished Professor
of Engineering and the director of the SRC Center of Excellence for Design
Dr. Brayton held the Edgar L. and Harold H. Buttner Endowed Chair
in Electrical Engineering at Berkeley.
He is a member of the National Academy of Engineering, and
a Fellow of the IEEE and the AAAS. He received the 1991 IEEE CAS
Technical Achievement Award, the CAS Golden Jubilee
IEEE Millennium Medals in 2000, and
the 1971 IEEE Guilleman-Cauer and 1987 ISCAS Darlington best paper
awards. He was the editor of the Journal on
Formal Methods in Systems Design from 1992-1996.
He has authored over 400 technical papers, and 8 books.
Past contributions have been in analysis of nonlinear networks,
electrical simulation and optimization of circuits, and asynchronous
synthesis. Current research involves combinational and sequential
logic synthesis for area/performance/testability, formal design verification
and logical/physical synthesis for DSM designs.
Randal E. Bryant received the B.S. degree in applied mathematics
from the University of Michigan, Ann Arbor in 1973, and the S.M.,
E.E., and Ph.D. degrees in electrical engineering and computer
science from the Massachusetts Institute of Technology, Cambridge in
1977, 1978, and 1981, respectively. He was on the faculty at the
California Institute of Technology from 1981 to 1984. Since
September, 1984 he has been at Carnegie Mellon University and is now
the President's Distinguished Professor of Computer Science. He also
holds a courtesy position in the Electrical and Computer Engineering
Department. He has been Head of the Computer Science Department
at Carnegie Mellon since September, 1999. He spent the 1990--1991
academic year as a Visiting Research Fellow at Fujitsu Laboratories,
His research and teaching interests include VLSI design, verification,
and testing, as well as algorithms and computer architecture. He
counts to his credit the following research achievements: the
formulation of conservative, asynchronous distributed simulation
(1977), formulation and implementation of the first switch-level
simulator (1979), the use of Ordered Binary Decision Diagrams (OBDDs)
for symbolic Boolean manipulation (1984), and the use of Binary Moment
Diagrams (BMDs) for verifying arithmetic circuits (1994).
Dr. Bryant received the 1987 CAD Transactions Best Paper Award, and
the 1989 Baker Prize from the IEEE. He was an Associate Editor for
IEEE Transactions on Computer-Aided Design for Integrated Circuits and
Systems from 1989 to 1995 and Editor-in-Chief from 1995 to 1997. He
was elected a Fellow of the IEEE in 1990, for ``contributions to
switch-level modeling of very-large-scale integrated circuits.'' He
was elected a Fellow of the ACM in 1999. Dr. Bryant has received
several awards from the Semiconductor Research Corporation: Inventor
recognition awards in 1989 and 1990, as well as a technical excellence
award (shared with Edmund M. Clarke and Ken McMillan) in 1996. He
received the ACM Kanellakis Theory and Practice Award (shared with
Edmund M. Clarke, Ken McMillan, and Allen Emerson) for contributing
to the development of symbolic model checking.
Maciej Ciesielski received the M.S. in Electrical Engineering from
Warsaw Technical University in 1974, and Ph.D. in Electrical
Engineering from the University of Rochester in 1983.
From 1983 to 1986 he was a Senior Member of Technical Staff
at GTE Laboratories, Waltham, MA, where he worked on silicon compilation
and layout synthesis projects.
Currently he is Associate Professor in the Department of Electrical and
Computer Engineering at the University of Massachusetts, Amherst.
He has performed research in the area of CAD for VLSI systems and circuit.
His specific research interests include: design validation and formal
verification; logic synthesis and optimization from behavioral and logic
specifications; physical design automation; and mathematical optimization
methods. He is a senior member of the IEEE.
Olivier Coudert joined Monterey Design Systems in 1998 to start the effort
logic synthesis and optimization. He is now a Senior Technologist and R\&D
Director, and has been working on flow issues mixing placement, timing,
synthesis, and routing. He has been driving and managing the timing,
synthesis, clock tree synthesis, and signal integrity activities.
He received his Ph.D. in computer sciences from Ecole Nationale
Superieure des Telecommunications (Paris, France) in 1991, and his
and M.S. degrees in computer sciences and applied mathematics from Ecole
Centrale de Paris (Paris, France) in 1987 and 1988. From 1994 to 1998 he
the Advance Technology Group of Synopsys, where he did product driven
development (low power optimization, formal verification) and prospective
research (logic synthesis, combinatorial optimization). From 1993 to 1994 he
was at DEC Paris Research Labs, where he mainly worked on formal
real-time software compilation, symbolic computation, logic synthesis, and
combinatorial optimization. From 1988 to 1993 he was at Bull Research
where he developed original verification methods for sequential systems, and
also worked on reliability analysis and logic minimization.
Dr. Olivier Coudert has (co)authored more than 50 international publications
formal verification, combinatorial and sequential logic synthesis,
combinatorial optimization, low power synthesis, and reliability analysis.
served on the technical program committee for several international
on CAD, including DAC, ICCAD, ED\&TC, EDAC, and CAV. He is a member of the
editorial board for "Formal Methods in System Design", Kluwer Pub. He
a best paper award at ICCD'90, ICCAD'90, DAC'92, ED\&TC'96, and DAC'96.
Giovanni De Micheli is Professor of Electrical Engineering, and by
of Computer Science at Stanford University.
His research interests include several aspects of design technologies
for integrated circuits and systems, with particular emphasis on
system-level design, hardware/software co-design and low-power design.
He is author of: Synthesis and Optimization of Digital Circuits,
1994, co-author and/or co-editor of five other books and of over 250
He is member of the technical advisory board of several EDA
companies, including Magma Design Automation, Coware and Aplus Design
He was member of the technical advisory board of Ambit Design Systems.
Dr. De Micheli is a Fellow of ACM and IEEE.
He received the Golden Jubilee Medal for outstanding contributions to
the IEEE CAS Society in 2000.
He received the 1987 IEEE Transactions on CAD/ICAS Best Paper Award
and two Best Paper Awards at the Design Automation Conference, in
1983and in 1993.
He is Editor in Chief of the IEEE Transactions on CAD/ICAS.
He was Vice President (for publications) of the IEEE CAS Society in
Dr. De Micheli was the Program Chair and General Chair of the
Design Automation Conference (DAC) in 1996-1997 and 2000 respectively.
He was also the Program and General Chair of the International
Conference on Computer Design (ICCD) in 1988 and 1989 respectively.
Elena Dubrova received the Diploma Engineer degree in
Computer Science from
Technical University of Sofia, Bulgaria, in 1993 and a Ph.D. in Computer
Science from University of Victoria, B.C., Canada, in 1997. Since 1998 she
has been an associate professor at the Department of Electronics at Royal
Institute of Technology, Stockholm, Sweden. Her research interest include
logic design, formal verification, fault-tolerant computing and and
multiple-valued logic. She has published over 40 international reviewed
technical papers in these areas and holds one patent. She served as
Co-Chair of IEEE CS Multiple-Valued Logic Technical Committee in 1999-2000
and as Program Chair for 29th International Symposium on Multiple-Valued
Logic in 1999. She received the IBM Faculty Partnership Award in 2000 and
Best Poster Award at Design and Test in Europe Conference DATE'2000.
She serves as an associate editor of the International Journal of
Multiple-Valued Logic. She is a member of the IEEE.
Cornelis (Koen) van Eijk received the Ir. degree in Information
Engineering and the Dr. degree in Electrical Engineering from the
Eindhoven University of Technology in 1992 and 1997 respectively. In
1997 he became an assistant professor in the Design Automation Section
of the Department of Electrical Engineering at the Eindhoven
University of Technology. His research topics included algorithms for
equivalence checking, high-level synthesis and compiler techniques for
embedded systems. In April 2000 he joined Magma Design Automation
where he continues to work on verification and synthesis of digital
Masahiro Fujita received his Ph.D. degree in Engineering from the
University of Tokyo in 1985 and then immediately joined Fujitsu
Laboratories Ltd. From 1993 to 2000, he had been assigned to Fujitsu's
US research office and directed the CAD research group. In March 2000,
he joined the department of Electronic Engineering in the University
of Tokyo as a professor. He has written over 100 technical papers on
all aspects of logic design CAD. He has received several awards from
Japanese major scientific societies on his works in formal
verification and logic synthesis. His doctor degree thesis was written
in early 80's and on model checking. Since then he has been involved
in many research projects on various aspects of formal verification and
Soha Hassoun is an assistant professor at Tufts University in the
Electrical Engineering and Computer Science Department. She earned a
Ph.D. from the Computer Science and Engineering Department at the
University of Washington, Seattle, in 1997. She received a BSEE from
South Dakota State University in 1986, and a Master's degree from MIT
in 1988. Prior to pursuing her Ph.D., Dr. Hassoun worked as a chip
designer in the microprocessor design group at Digital Equipment
Corporation. She was one of the 21064 Alpha processor's main circuit
designers. She also designed a commercial cache controller for the VAX
6400, a vector processor, a 3-transistor dynamic RAM, and a router
Dr. Hassoun's research includes CAD, VLSI design, and computer
architecture. Recent interests include timing, logical, and physical
verification for deep submicron circuits; designing network
processors; and system-level design and optimization tools for
Dr. Hassoun is an NSF CAREER award recipient. In June 2000, she
received the ACM/SIGDA Distinguished Service Award for creating the
Ph.D. forum at DAC. Dr. Hassoun serves on the advisory board for ACM's
Special Interest Group on Design Automation (SIGDA). She was program
and publicity chair for the International Workshop on Logic Synthesis,
June 2001. She is a Tau Beta Pi Fellow. She is a member of ACM, IEEE,
and Eta Kappa Nu.
Andreas Kuehlmann received the Dipl-Ing. degree and the Dr.-Ing. habil degree in Electrical Engineering from the University of Technology at
Ilmenau, Germany, in 1986 and 1990, respectively. His research topics
included algorithms for automatic layout verification and synthesis.
From 1990 to 1991 he worked at the Fraunhofer Institute of
Microelectronic Circuits and Systems, Duisburg, on a project to
automatically synthesize embedded microcontrollers. In 1991 he joined
the IBM T.J. Watson Research Center where he worked until June 2000 on
various projects in high-level and logic synthesis and hardware
verification. Among others, he was the principal author and project
leader of Verity, IBMs standard equivalence checking tool. In July
2000 he joined the Cadence Berkeley Labs where he continues to work on
synthesis and verification problems.
Yuji Kukimoto received the B.S. and the M.S. degrees in electrical
engineering and in computer science from the University of Tokyo
in 1989 and 1991 respectively, and the Ph.D. degree in electrical
engineering and computer science from University of
California, Berkeley in 1998. He was with Strategic CAD Laboratories
of Intel Corporation, Hillsboro, OR from 1998 to 1999, and with
Monterey Design Systems, Sunnyvale, CA from 1999 to 2000.
He is currently a member of technical staff at Silicon Perspective
Corporation, Santa Clara, CA. His research interests include logic
synthesis, physical synthesis, static timing analysis and formal
verification. He has published more than 20 papers on these topics.
He has served on the program committees of various conferences
such as International Conference on Computer-Aided Design (ICCAD),
Asian and South Pacific Design Automation Conference (ASPDAC) and
ACM International Workshop on Timing Issues in the Specification and
Synthesis of Digital Systems.
Wolfgang Kunz obtained the Dipl.Ing. degree of electrical engineering from
University of Karlsruhe in 1989 and the doctor's degree from University of
Hannover in 1992. From 1989 to 1991 he was a graduate student at the ECE
Department at the University of Massachusetts at Amherst. From 1993 to
1998 he was with Max-Planck Fault-Tolerant Computing Group at the
University of Potsdam. Since 1998 he is a professor at the CS Department
at University of Frankfurt/Main.
Wolfgang Kunz conducts research in the areas of logic and layout
synthesis, equivalence checking and ATPG. For his contributions in these
areas he has received several awards including the IEEE Transactions on
CAD Best Paper Award.
Luciano Lavagno graduated magna cum laude
in Electrical Engineering from Politecnico di Torino (Italy) in 1983.
From 1984 to 1988 he was with CSELT Laboratories (Torino, Italy), where
he was involved in the ESPRIT 802 CVS project that developed a complete
high-level synthesis system.
In 1988 he joined the Department of Electrical Engineering and Computer Science
of the University of California at Berkeley, where he worked on logic
synthesis and testing of synchronous and asynchronous circuits.
In 1992 he received his Ph.D. in Electrical Engineering and Computer Science
from the University of California at Berkeley.
Between 1993 and 1998 he was an Assistant Professor with the Department of
Electronics of Politecnico di Torino.
Since 1993 he has been the architect of the POLIS project
(a cooperation between U.C. Berkeley, Cadence
Design Systems, Magneti Marelli and Politecnico di Torino), developing a
complete hardware/software co-design environment for control-dominated embedded
systems. POLIS is one of the
basic technologies behind the Cierto VCC system-level design and IP integration
tool by Cadence Design Systems.
Since 1994 he has been a research scientist at Cadence Berkeley Laboratories.
Since 1997 he has participated in the ESPRIT 25443 COSY project, developing
(based on the POLIS and VCC technologies) a methodology for software
synthesis and performance analysis for embedded systems.
Since 1998 he has been an Associate Professor with the Department of
Electrical, Management and Mechanical Engineering (DIEGM) of the University
of Udine, Italy.
His research interests include the synthesis of asynchronous and
low-power circuits, the concurrent design of mixed hardware and software
systems, and the formal verification of digital systems.
Dr. Lavagno is the author of a book on asynchronous circuit design, the
co-author of a book on hardware/software co-design of embedded systems, and has
published over 80 journal and conference papers.
In 1991 he received the Best Paper award at the Design Automation
Conference in San Francisco, CA. He has served on the technical committees of
conferences in his field (namely the Design
Automation Conference, the International Conference on Computer Aided
Design, the conference on
Design Automation and Test in Europe). He has also served as
technical committee member or chair of several workshops and symposia
(for example, the International Symposium
on Asynchronous Circuits and Systems, the International Workshop
on Hardware-Software Co-Design, the International Workshop on Logic
Synthesis). He has been a consultant for various EDA companies, such as
Synopsys and Cadence.
Sharad Malik received the B. Tech. degree in Electrical Engineering
from the Indian Institute of Technology, New Delhi, India in 1985
and the M.S. and Ph.D. degrees in Computer Science from the University
of California, Berkeley in 1987 and 1990 respectively.
Currently he is Professor in the Department of Electrical
Engineering, Princeton University. His current research interests are:
design tools for embedded computer systems, synthesis and verification
of digital systems.
He has received the President of India's Gold Medal for academic
excellence (1985), the IBM Faculty Development Award (1991), an NSF
Research Initiation Award (1992), Princeton University Rheinstein Faculty
Award (1994), the NSF Young Investigator Award (1994), Best Paper Award
at the IEEE International Conference on Computer Design (1992) and at
the ACM/IEEE Design Automation Conference (1996), the Walter C. Johnson
Prize for Teaching Excellence (1993) and the Princeton University
Engineering Council Excellence in Teaching Award (1993, 1994, 1995).
He serves/has served on the program committees of DAC, ICCAD and ICCD.
He is serving as the technical program co-chair for DAC in 2000 and 2001.
He is on the editorial boards of the Journal of VLSI Signal Processing
and Design Automation for Embedded Systems.
Joao Marques-Silva obtained the BSc and MSc degrees at the Technical
University of Lisbon, Portugal, in 1988 and 1991, respectively, and
the PhD degree at the University of Michigan, Ann Arbor, in 1995.
Since 1995, he has been an Assistant Professor at the Computer Science
Department of the Technical University of Lisbon, Portugal, and a
member of the Cadence European Laboratories. His research research
interests include Algorithms for Discrete Optimization Problems,
namely Satisfiability, Unate/Binate Covering and Integer Programming,
and Applications of Discrete Optimization in EDA.
Yusuke Matsunaga received B.E. ,M.E and Ph.D. degrees in Electronics
and Communication Engineering from Waseda University, Tokyo, Japan,
in 1985, 1987 and 1997, respectively.
He joined Fujitsu Laboratories in Kawasaki, Japan, in 1987 and he has
been involved in research and development of the CAD for digital
systems. From October 1991 to November 1992, he has been a Visiting
Industrial Fellow at the University of California, Berkeley, in the
department of Electrical Engineering and Computer Sciences. In 2001,
he joined the faculty at Kyushu University.
He is currently an associate professor of the department of Computer
Science and Communication Engineering.
His research interest includes logic synthesis, formal verification,
high-level synthesis and automatic test pattern generation.
He is a member of IEEE.
Christoph Meinel is full professor (C4) for computer
science at the department of computer sciences at the University of
Trier in Germany.
Christoph Meinel studied from 1974-79 Mathematics and Computer Science
at the Humboldt-University in Berlin. He received his PhD degree in 1981.
From 1981-1991 he worked at the Department of Mathematics at the
Humboldt University and at the Institute of Mathematics of the Academy
of Sciences in Berlin as a scientific assistant. 1988 he received his habilitation degree with a paper about complexity theory that was published as a
monograph in the Lecture Notes of Computer Science Series (Volume 370)
of the Springer-Verlag. After a research stay at the University of
Saarbr\"ucken and a visiting position at the University of Paderborn 1992
he became a full professor for computer science at the university of
Christoph Meinel is author, co-author or editor of 9 books and has
published more than 100 papers in highly recommended scientific journals
and international congresses. Most of his lecture notes are available
via the internet. His main research interests are now VLSI-design,
telematics and complexity theory.
Since 1998 he is the founding director of the independent research
institut Institut f\"ur Telematik (TI) in Trier. The special expertise of
this institute lies on the following fields: Electronic publishing,
security in open nets and telemedicine. The Institut f\"ur Telematik is
organized like the institutes of the famous Fraunhofer society. Two
thirds of the institute's budget come from research projects from
industry and business. Today there are employed about 50 scientific
coworkers, doctorands, technical staff and practicants.
Beside Christoph Meinel is the editor in chief of the Electronic
Colloquium on Computational Complexity and a member of different
and international program committees. E.g. he was the chairman of the
international symposium of Theoretical Aspects in Computer Science,
STACS'99, that was held 1999 in Trier. He is the organizer of the
serious of the Trierer Symposia on various actual fields of telematics. He
belongs to the directory board of the international conference and research
center for computer science IBFI in Schloss Dagstuhl and is the speaker
of the special interest group Complexity of the German society of
Rajeev Murgai received the Bachelor of Technology (with the highest
honors) in Electrical Engineering from the Indian Institute of
Technology Delhi in 1987, Masters of Science in Electrical and Computer
Engineering from Carnegie Mellon University in 1989, and Ph.D. from
the University of California at Berkeley in December 1993 in
Electrical Engineering and Computer Sciences. Since 1994, he has been
at Fujitsu Laboratories of America, Inc., where he is a Project Leader
of the Performance Optimization Group in the Advanced CAD Research
Department. He has over 30 publications in
the areas of logic synthesis, FPGAs, timing optimization, physical
design, circuit partitioning, logic simulation, and formal
verification. He has authored the book "Logic Synthesis for
Field-Programmable Gate Arrays," published in 1995. He has served on the
Technical Program Committees of ICCAD, DATE, ASP-DAC, and IWLS.
Steven M. Nowick is an Associate Professor of Computer Science at
Columbia University. He received a Ph.D. in Computer Science from
Stanford University in 1993, and a B.A. from Yale University.
His Ph.D. dissertation introduced an automated synthesis method
for locally-clocked asynchronous state machines, and he formalized
the asynchronous specification style called ``burst mode''. His
research interests include asynchronous circuits, CAD, low-power
and high-performance digital systems, logic synthesis, and formal
verification of finite-state concurrent systems.
He is the recipient of two two large-scale NSF ITR awards (2000)
for research on asynchronous design, both on CAD tools
for large-scale asynchronous systems
as well as for high-speed and low-power asynchronous 3G wireless design.
He has received an NSF Faculty Early Career (CAREER) Award (1995),
an Alfred P. Sloan Research Fellowship (1995) and an NSF Research
Initiation Award (RIA) (1993). He received a Best Paper Award
at the 2000 IEEE Async Symposium and the 1991 IEEE International Conference
on Computer Design, and was a Best Paper Finalist at the 1993 Hawaii
International Conference on System Sciences and at the 1998 IEEE
He was co-founder and Program Committee Co-Chair of the 1st IEEE Async
Symposium (1994), and was Program Committee Co-Chair of the
5th IEEE Async Symposium (1999). He has been a member of 25
international program committees, including ICCAD, DATE, ICCD, Async,
TAU, VLSI Design and ARVLSI.
He was Guest Editor of a special issue of the journal,
``Proceedings of the IEEE'' (v. 87:2, Feb. 1999), on asynchronous
circuits and systems. He is also co-author, with Robert Fuhrer, of
the Kluwer book,
``Sequential Optimization of Asynchronous and Synchronous Finite-State
Machines: Algorithms and Tools'' (2001).
Karem A. Sakallah received the B.E. degree (with
distinction) in electrical engineering from the American University of
Beirut, Beirut, Lebanon, in 1975, and the M.S.E.E. and Ph.D. degrees in
electrical and computer engineering from Carnegie Mellon University,
Pittsburgh, PA, in 1977 and 1981, respectively.
In 1981 he joined the Department of Electrical Engineering at CMU as a
Visiting Assistant Professor. From 1982 to 1988 he was with the
Semiconductor Engineering Computer-Aided Design Group at Digital Equipment
Corporation in Hudson, Massachusetts, where he headed the Analysis and
Simulation Advanced Development team. Since September 1988 he has been at
the University of Michigan, Ann Arbor, MI, as Professor of Electrical
Engineering and Computer Science. From September 1994 to March 1995, he was
on a six-month sabbatical leave at the Cadence Berkeley Laboratory in
Berkeley, California. He was associate editor of the IEEE Transactions on
CAD during 1995-1997, and has served on the program committees of ICCAD,
DAC, ICCD, and numerous other workshops. He has published more than 120
papers, and has presented seminars and tutorials at many professional
meetings and various industrial sites. His research interests are primarily
in the area of computer-aided design, with particular emphasis on
simulation, timing verification and optimal clocking, modeling, synthesis,
knowledge abstraction, and design environments.
Karem Sakallah is a fellow of the IEEE and a member of the ACM and Sigma Xi.
Tsutomu Sasao received the B.E., M.E., and Ph.D. degrees in Electronics
Engineering from Osaka University, Osaka Japan, in 1972, 1974, and 1977,
He has held faculty/research positions at Osaka University, Japan,
IBM T. J. Watson Research Center, Yorktown Height, NY and
the Naval Postgraduate School, Monterey, CA.
Now, he is a Professor of Department of Computer Science and Electronics,
as well as the Director of the Center for Microelectronic
Systems at the Kyushu Institute of Technology, Iizuka, Japan.
His research areas include logic design and switching theory,
representations of logic functions, and multiple-valued logic.
He has published more than 8 books on logic design including,
Logic Synthesis and Optimization, Representation of Discrete Functions,
Switching Theory for Logic Synthesis,
Kluwer Academic Publishers 1993, 1996, 1999, respectively.
He has served Program Chairman for the IEEE International Symposium
on Multiple-Valued Logic (ISMVL) many times. Also, he was the Symposium
Chairman of the 28th ISMVL held in Fukuoka, Japan in 1998.
He received the NIWA Memorial Award in 1979, and Distinctive Contribution
Awards from IEEE Computer Society MVL-TC in 1987 and 1996 for papers
presented at ISMVLs. He has served an associate editor of the
IEEE Transactions on Computers. He is a Fellow of the IEEE.
Ellen M. Sentovich received the B.S., M.S., and Ph.D. degrees in
Electrical Engineering and Computer Science from the University
of California Berkeley in 1985, 1988, and 1993. She consulted for
Intel in Haifa, Israel, before joining INRIA, the French National
Computer Science Research Laboratory, as a postdoctoral fellow.
She spent 1.5 years at INRIA, working on synthesis from synchronous
language specifications. Since returning, she has been at Cadence
Berkeley Laboratories. Her research interests include system-level
specification, synchronous languages and design of synchronous systems,
and many areas related to system-level design, including models of
computation, logic synthesis, software synthesis, and verification.
She has recently served as technical chair and general chair of
ICCAD, the International Conference on Computer-Aided Design.
Leon Stok studied electrical engineering at Eindhoven University of
Technology, the Netherlands, from which he graduated with honors on
August 28, 1986. In July 1991 he obtained a Ph.D. degree from the
Eindhoven University. In July 1991, Leon Stok started working in the
Computer Science Department of IBM's Thomas J. Watson Research Center
on BooleDozer, the IBM logic synthesis Tool. After that he managed the
logic synthesis group. He is currently Senior Manager Design
Automation in the Systems Department.
Mr. Stok has published several papers on the various aspects of high
level, architectural and logic synthesis, placement driven synthesis
and on the automatic placement and routing for schematic
diagrams. Mr. Stok has given tutorials on the various aspects of
synthesis at the mayor DA conferences (EDAC91, DAC92, EuroDac97,
ICCAD97, ICCAD00). His research interests include high-level and logic
synthesis, layout synthesis and systems synthesis and verification. He
is a senior member of the Institute of Electrical and Electronics
received a B. Tech degree in Computer Science and Engineering from
the Indian Institute of Technology, New Delhi, India in 1991, and a Ph.D. in
Electrical Engineering from Princeton University in 1996. He is currently
the Operations Program Manager for the Pentium (R) 4 Processor at Intel
He is also affiliated with the Low Power Design Technology (LPDT) group, a
where he worked full-time till December 2000. The charter of the group is to
power in Intel's high-end microprocessors. This involves the research and
development of techniques and methodologies for power reduction at the
logic and architecture levels, and the productization of these for next
generation Intel CPUs. Vivek was primarily responsible for Tools and
and subsequently managed LPDT. He has also held research positions at NEC
Labs (1992), Fujitsu Labs of America (1994), and IBM T. J. Watson Research
(1995), while pursuing the doctoral degree. He received the IBM Fellowship
and a Best Paper Award at ASP-DAC '95. He has served on the Technical and
Committee of the International Symposium on Low Power Electronics and Design
on the Technical Program Committees of the Design Automation Conference, and
VLSI Design Conferences.
Tiziano Villa studied mathematics at the universities of Milano,
Cambdrige, U.K. and electrical engineering and computer science at
the University of California, Berkeley, where he completed a Ph.D. in EECS
He worked in the integrated circuits division of the CSELT Labs,
Torino Italy, as a computer-aided design specialist, and then for some
years he was a research assistant at the Electronics Research
Laboratory, University of California, Berkeley. In 1997 he joined as
a Research Scientist the PARADES Labs, Rome, Italy, a research
consortium participated by Cadence Design Systems, Magneti-Marelli,
ST-Microlelectronics and CNR (Italian National Research Council).
His research interests include logic synthesis, formal verification,
combinatorial optimization, automata theory and hybrid systems.
His contributions are mainly in the areas of combinational and sequential
logic synthesis and of analysis and synthesis of hybrid systems.
In May 1991 he was awarded the Tong Leong Lim Pre-doctoral Prize at the EECS
Department of the University of California, Berkeley.
He co-authored the books ``Synthesis of FSMs: functional optimization'',
Kluwer, 1997 and ``Synthesis of FSMs: logic optimization'', Kluwer 1997.